PM7347 datasheet(188/341 Pages) PMC

188 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

188

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

FULL

Bit 5

BLFILL

Bit 4

Unused

Bit 3

FULLI

Bit 2

OVRI

Bit 1

UDRI

Bit 0

LFILLI

Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR

Transmit Data Register and reads of the TDPR Interrupt Status/UDR Clear Register should not

occur at rates greater than 1/8th that of the clock selected by the LINESYSCLK bit of the S/UNI-

JET Miscellaneous Register (39BH).

LFILLI

The LFILLI bit will transition to logic one when the TDPR FIFO level transitions to empty or

falls below the value of LINT[6:0] programmed in the TDPR Lower Interrupt Threshold

one. LFILLI is cleared when this register is read.

UDRI

The UDRI bit will transition to logic one when the TDPR FIFO underruns. That is, the TDPR

is in the process of transmitting a packet when it runs out of data to transmit. UDRI will

assert INTB if it is a logic one and UDRE is programmed to logic one. UDRI is cleared when

this register is read.

OVRI

The OVRI bit will transition to logic one when the TDPR FIFO overruns. That is, the TDPR

FIFO is already full when another data byte is written to the TDPR Transmit Data Register.

OVRI will assert INTB if it is a logic one and OVRE is programmed to logic one. OVRI is

cleared when this register is read.

FULLI

The FULLI bit will transition to logic one when the TDPR FIFO is full. FULLI will assert

INTB if it is a logic one and FULLE is programmed to logic one. FULLI is cleared when this

PM7347 Datasheet(PDF) 188 Page - PMC-Sierra, Inc

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