PM8621 datasheet(114/184 Pages) PMC

114 / 184 page

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

113

Document ID: PMC-2010850, Issue 1

Bit

Type

Function

Default

Bit 31:16

Unused

Bit 15

TX_MSG_LVL_VALID

N/A

Bit 14:13

TX_LINK[1:0]

Bit 12:11

IPAGE[1:0]

N/A

Bit 10:8

IUSER[2:0]

N/A

Bit 7:6

Reserved

Bit 5:2

TX_MSG_LVL[3:0]

0000

Bit 1

TX_FI_BUSY

Bit 0

TX_XFER_SYNC

This register serves a dual purpose dependant on whether it is being read or written.

When it is read it returns the status for the Message Transmit Channel.

When it is written (with 0001h) to it is used it synchronize the Transmit FIFO to the start of a

message boundary.

TX_XFER_SYNC

Writing ‘1’ to this bit initializes the next write sequence to be to the beginning of the next

message. After a ‘1’ had been written successive writes to the Transmit FIFO will be to

location zero of the next available slot. If a partial message has been written,

TX_XFER_SYNC indicates that the current message is complete and that subsequent writes

will be to the next message. If more than 32 bytes are written, the 33rd byte will be the first

byte of the next message. The purpose of this bit is to unambiguously align the message

boundaries. Another use would be to abandon the current write and move the write pointer to

the beginning of the next message. (Previous message data will remain in the unwritten

portion of the message being abandoned, which will have to be ignored by the receiving

software).

If the message FIFO pointers are already at a message boundary then writing this bit to a ‘1’

will have no affect.

On reads this bit is always returned as a ‘0’.

TX_FI_BUSY

This bit indicates that the internal hardware is transferring the data from the Transmit FIFO

registers (TDAT) into the internal RAM. This bit need not be read by software if the time

interval between successive 32 bit transfers is greater than 3 SYSCLK cycles.

User and Page bits are a copy of the User bits received, and being transmitted in 0Ch. These

allow one read in the 32 bit device to gain a snapshot of the entire ILC.

PM8621 Datasheet(PDF) 114 Page - PMC-Sierra, Inc

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