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PM8621 Datasheet(PDF) 111 Page - PMC-Sierra, Inc |
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PM8621 Datasheet(HTML) 111 Page - PMC-Sierra, Inc |
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111 / 184 page ![]() NSE-8G™ Standard Product Data Sheet Preliminary Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 110 Document ID: PMC-2010850, Issue 1 Register 10DH + N*20H, TXLV and PISO Control Bit Type Function Default Bit 31:12 Unused X Bit 11 Reserved[8] 0 Bit 10 R/W Reserved[7] 0 Bit 9 R/W Reserved[6] 0 Bit 8 R/W TXLV_ENB 0 Bit 7 R/W PISO_ENB 0 Bit 6 R/W Reserved[5] 0 Bit 5 R/W Reserved[4] 0 Bit 4 R/W Reserved[3] 0 Bit 3 R/W Reserved[2] 0 Bit 2 R/W Reserved[1] 1 Bit 1 R/W Reserved[0] 1 Bit 0 R/W ARSTB 1 ARSTB The analog reset bit (ARSTB) resets the associated TXLV and PISO blocks. When ARSTB is set to logic 0, the TXLV and PISO are reset. Reserved[5:0] The Reserved[3:0] bits must be set to the indicated default value for correct operation of the NSE. PISO_ENB The PISO enable bit (PISO_ENB) controls the operation of the PISO block. PISO_ENB is set to logic one to disable the PISO block. PISO_ENB is set to logic 0 to enable the PISO block. TXLV_ENB The TXLV enable bit (TXLV_ENB) controls the operation of TXLV block. TXLV_ENB is set to logic one to disable the TXLV block. TXLV_ENB is set to logic 0 to enable the TXLV block. Reserved[8] The Reserved[8] bit must be set to the indicated default value for correct operation of the NSE. |
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