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PM8621 Datasheet(PDF) 165 Page - PMC-Sierra, Inc

Part # PM8621
Description  NSE-8G??Standard Product Data Sheet Preliminary
PDF  184 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM8621 Datasheet(HTML) 165 Page - PMC-Sierra, Inc

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NSE-8G™ Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
164
Document ID: PMC-2010850, Issue 1
12.14.1 TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary
input, TCK. All state transitions are controlled using primary input, TMS. The finite state
machine is described below.
Figure 35 TAP Controller Finite State Machine
Test-Logic-Reset
Run-Test-Idle
Select-DR-Scan
Select-IR-Scan
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Exit1-DR
Exit1-IR
Pause-DR
Pause-IR
Exit2-DR
Exit2-IR
Update-DR
Update-IR
TRSTB=0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
All transitions dependent on input TMS
0
0
0
0
0
1
12.14.2 States
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode
operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered
synchronously regardless of the current TAP controller state by forcing input, TMS high for 5
TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.



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