PM8621 datasheet(168/184 Pages) PMC

168 / 184 page

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

167

Document ID: PMC-2010850, Issue 1

Functional Timing

13.1

Receive Interface Timing

Figure 35 below, shows the relative timing of the receive interface. The LVDS links carry

SONET/SDH frame octets that are encoded in 8B/10B characters. Frame boundaries, justification

events and alarm conditions are encoded in special control characters. The upstream devices

sourcing the links share a common clock and have a common transport frame alignment that is

synchronized by the Receive Serial Interface Frame Pulse signal (RC1FP). Due to phase noise of

clock multiplication circuits and backplane routing or cable length discrepancies, the links will

not phase aligned to each other but are frequency locked. The delay from RC1FP being sampled

high to the first and last C1 character is shown in Figure 35 In this example, the first C1 is

delivered on link RN[X]/RP[X]. The delay to the last C1 represents the time when the all the

links have delivered their C1 character. In the example below, link RN[Y]/RP[Y] is shown to be

the slowest. The minimum value for the internal programmable delay (RC1DLY[13:0]) is the

delay through the SBS2 plus 15. The maximum value is the delay through the SBS plus 31.

Consequently, the external system must ensure that the relative delays between all the receive

LVDS links be less than 16 bytes. The relative phases of the links in Figure 35 are shown for

illustrative purposes only. Links may have different delays relative to other links than what is

shown.

Figure 36 Receive Interface Timing

RP[X]/

RN[X]

RN[Y]/

RP[Y]

...

SYSCLK

RC1FP

S4,3/

S1,1/

S2,1/

S4,3/

S1,1/

S2,1/

RC1DLY[13:0] Delay

...

Max Delay between

First and Last J0s

Max Delay until internal Frame Pulse

...

Min Delay until internal

Frame Pulse

2 This delay will be either one frame (9720 clock cycles) or one row (1080 clock cycles)

depending on the mode employed.

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