PM8621 datasheet(169/184 Pages) PMC

169 / 184 page

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

168

Document ID: PMC-2010850, Issue 1

13.2

Transmit Interface Timing

Figure 36 below shows the delay from assertion of RC1FP to the transmit serial data links. Due to

the presence of FIFOs in the data path, the delay to the various links can differ by up to eight

cycles. The minimum delay (RC1DLY + 43 SYSCLK cycles) is shown to be incurred by one of

the transmit protect serial data links (TP[X]/TN[X]). The maximum delay (RC1DLY + 51 cycles)

is shown to be incurred by one of the transmit auxiliary serial data links (TP[Y]/TN[Y]). The

suggested setting for TC1DLY results in a TC1FP pulse at the time at which all the transmit serial

links have transmitted their respective C1 characters. The maximum delay from RC1FP to the

transmission of a C1 pulse is RC1DLY + 52 cycles. Therefore the suggested setting for TC1DLY

is RC1DLY+ 52. Figure 36 shows the timing of TC1FP with the suggested setting for TC1DLY.

The relative phases of the links in Figure 36 are shown for illustrative purposes only. Links may

have different delays than what is shown.

Figure 37 Transmit Interface Timing

TP[X]/

TN[X]

TN[Y]/

TP[Y]

...

SYSCLK

RC1FP

S4,3/

S1,1/J0

S2,1/

S4,3/

S1,1/

S2,1/

RC1DLY+ Max Delay(51 cycles) to Last C1

...

RC1DLY + Min Delay(43

cycles) to First C1

...

TC1FP

...

TC1DLY (RC1DLY + Delay to TC1FP(52 cycles))

Figure 37 below shows the delay from CMP to the transmit serial data links. CMP is valid only at

the RC1FP pulse time, whether RC1FP is pulsed or not. It is ignored at other locations in the

transport frame. A change in value to the connection memory page signal (CMP) results in

changing the active switch settings. Given that CMP is sampled on the RC1FP pulse time, the

first data that is switched according to the newly selected connection memory page are the first

A1 bytes of the frame following the C1 bytes transmitted by the NSE-8G before offset RC1DLY

+ 52 cycles. In more absolute terms, the first A1s transmitted by the NSE-8G between offset

RC1DLY + 43 + 9696 cycles and RC1DLY + 51 + 9696 cycles, represent the first data switched

according the connection memory page selected by CMP at the RC1FP pulse time.

PM8621 Datasheet(PDF) 169 Page - PMC-Sierra, Inc

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