PM8621 datasheet(176/184 Pages) PMC

176 / 184 page

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

175

Document ID: PMC-2010850, Issue 1

Table 18 Microprocessor Interface Write Access

Symbol

Parameter

Min

Max

Units

tSAW

Address to Valid Write Set-up Time

tSDW

Data to Valid Write Set-up Time

tSALW

Address to Latch Set-up Time

tHALW

Address to Latch Hold Time

tVL

Valid Latch Pulse Width

tSLW

Latch to Write Set-up

tHLW

Latch to Write Hold

tHDW

Data to Valid Write Hold Time

tHAW

Address to Valid Write Hold Time

tVWR

Valid Write Pulse Width

Figure 40 Microprocessor Interface Write Timing

VALID

tHdw

tSdw

tVwr

tSlw

tHalw

tVl

tSalw

tVl

tHaw

tSaw

A[11:0]

ALE

CSB+WRB)

D[31:0]

Notes on Microprocessor Interface Write Timing:

A valid write cycle is defined as a logical OR of the CSB and the WRB signals.

In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW,

tHALW, tVL, tSLW, and tHLW are not applicable.

Parameter tHAW is not applicable if address latching is used.

When a set-up time is specified between an input and a clock, the set-up time is the time in

nanoseconds from the 1.4 V point of the input to the 1.4 V point of the clock.

When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds

from the 1.4 V point of the input to the 1.4 V point of the clock.

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