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C8051F360 Datasheet(PDF) 75 Page - Silicon Laboratories |
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C8051F360 Datasheet(HTML) 75 Page - Silicon Laboratories |
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75 / 288 page  Rev. 1.0 75 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge interrupt enabled. Bit 4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable. 0: Comparator0 Falling-edge interrupt disabled. 1: Comparator0 Falling-edge interrupt enabled. Bits 3–2: UNUSED. Read = 00b, Write = don’t care. Bits 1–0: CP0MD1–CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. SFR Page: SFR Address: all pages 0x9D R R R/W R/W R R R/W R/W Reset Value –– CP0RIE CP0FIE –– CP0MD1 CP0MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Mode CP0MD1 CP0MD0 CP0 Response Time (TYP) 000 100 ns 101 175 ns 210 320 ns 3 1 1 1050 ns |
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