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C8051F360 Datasheet(PDF) 78 Page - Silicon Laboratories |
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C8051F360 Datasheet(HTML) 78 Page - Silicon Laboratories |
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78 / 288 page  C8051F360/1/2/3/4/5/6/7/8/9 78 Rev. 1.0 SFR Definition 8.6. CPT1MD: Comparator1 Mode Selection Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 Rising-edge interrupt disabled. 1: Comparator1 Rising-edge interrupt enabled. Bit 4: CP1FIE: Comparator1 Falling-Edge Interrupt Enable. 0: Comparator1 Falling-edge interrupt disabled. 1: Comparator1 Falling-edge interrupt enabled. Bits 3–2: UNUSED. Read = 00b, Write = don’t care. Bits 1–0: CP1MD1–CP1MD0: Comparator1 Mode Select These bits select the response time for Comparator1. SFR Page: SFR Address: all pages 0x9C R R R/W R/W R R R/W R/W Reset Value –– CP1RIE CP1FIE –– CP1MD1 CP1MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Mode CP1MD1 CP1MD0 CP1 Response Time (TYP) 0 0 0 100 ns 1 0 1 175 ns 2 1 0 320 ns 3 1 1 1050 ns |
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