C8051F360 datasheet(28/288 Pages) SILABS

28 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

Rev. 1.0

cated by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC

data SFRs upon completion of a conversion.

Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is

either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-

ground mode, but not interrupt the controller unless the converted data is within/outside the specified

range.

ADC0CF

10-Bit

SAR

ADC

ADC0CN

Timer 0 Overflow

Timer 2 Overflow

Timer 1 Overflow

Start

Conversion

000

AD0BUSY (W)

VDD

ADC0LTH

23-to-1

AMUX

AD0WINT

Temp

Sensor

23-to-1

AMUX

VDD

P1.0

P1.7

001

010

011

100

CNVSTR Input

Window

Compare

Logic

P2.0

P2.7

GND

P1.0

P1.7

P2.0

P2.7

P3.0

P3.4

101

Timer 3 Overflow

ADC0LTL

ADC0GTH ADC0GTL

AMX0P

AMX0N

P3.0

P3.4

P3.1-3.4 available on

C8051F360/1/6/8

(+)

(-)

VREF

P3.1-3.4 available on

C8051F360/1/6/8

P1.0-1.3 available on

C8051F361/2/6/7/8/9

P1.0-1.3 available on

C8051F361/2/6/7/8/9

Figure 1.11. 10-Bit ADC Block Diagram

1.8.

Comparators

C8051F36x devices include two on-chip voltage comparators that are enabled/disabled and configured via

user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator

outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output.

Comparator response time is programmable, allowing the user to select between high-speed and low-

power modes. Positive and negative hysteresis are also configurable.

Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-

rupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.

Figure 1.12 shows the Comparator0 block diagram, and Figure 1.13 shows the Comparator1 block dia-

gram.

Note: The first Port I/O pins shown in Figure 1.12 and Figure 1.13 are for the 48-pin (C8051F360/3)

devices. The second set of Port I/O pins are for the 32-pin and 28-pin (C8051F361/2/4/5/6/7/8/9) devices.

Please refer to the CPTnMX registers (SFR Definition 8.2 and SFR Definition 8.5) for more information.

C8051F360 Datasheet(PDF) 28 Page - Silicon Laboratories

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