C8051F360 datasheet(26/288 Pages) SILABS

26 / 288 page

C8051F360/1/2/3/4/5/6/7/8/9

Rev. 1.0

The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See Figure 1.8.)

On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the

controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This

allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the

particular application.

XBR0, XBR1,

PnSKIP Registers

Digital

Crossbar

Priority

Decoder

I/O

Cells

P0.0

P0.7

P0MASK, P0MATCH

P1MASK, P1MATCH,

P2MASK, P2MATCH

Registers

UART

Highest

Priority

Lowest

Priority

SYSCLK

SMBus

T0, T1

PCA

CP0

CP1

Outputs

SPI

(P0.0-P0.7)

(P1.0-P1.7)

(P2.0-P2.7)

PnMDOUT,

PnMDIN Registers

3.5–3.7 available on

C8051F360/3

(P3.0-P3.7)

I/O

Cells

P1.0

P1.7

I/O

Cell

P2.0

P2.7

I/O

Cells

P3.0

P3.7

3.1–3.4 available on

C8051F360/1/3/4/6/8

Figure 1.8. Digital Crossbar Diagram (Port 0 to Port 3)

1.5.

Serial Ports

The C8051F36x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate

configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware

and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.

1.6.

Programmable Counter Array

An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-

pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three program-

mable capture/compare modules. The PCA clock is derived from one of six sources: the system clock

divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system

clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for

C8051F360 Datasheet(PDF) 26 Page - Silicon Laboratories

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