C8051F360 datasheet(85/288 Pages) SILABS

85 / 288 page

Rev. 1.0

C8051F360/1/2/3/4/5/6/7/8/9

JZ rel

Jump if A equals zero

2/3*

JNZ rel

Jump if A does not equal zero

2/3*

CJNE A, direct, rel

Compare direct byte to A and jump if not equal

3/4*

CJNE A, #data, rel

Compare immediate to A and jump if not equal

3/4*

CJNE Rn, #data, rel

Compare immediate to Register and jump if not

equal

3/4*

CJNE @Ri, #data, rel

Compare immediate to indirect and jump if not

equal

4/5*

DJNZ Rn, rel

Decrement Register and jump if not zero

2/3*

DJNZ direct, rel

Decrement direct byte and jump if not zero

3/4*

NOP

No operation

* Branch instructions will incur a cache-miss penalty if the branch target location is not already stored in

the Branch Target Cache. See Section “14. Branch Target Cache” on page 145 for more details.

Notes on Registers, Operands and Addressing Modes:

Rn - Register R0-R7 of the currently selected register bank.

@Ri - Data RAM location addressed indirectly through R0 or R1.

rel - 8-bit, signed (2s complement) offset relative to the first byte of the following instruction. Used by

SJMP and all conditional jumps.

direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-

0x7F) or an SFR (0x80-0xFF).

#data - 8-bit constant

#data16 - 16-bit constant

bit - Direct-accessed bit in Data RAM or SFR

addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same

2K-byte page of program memory as the first byte of the following instruction.

addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within

the 64K-byte program memory space.

There is one unused opcode (0xA5) that performs the same function as NOP.

Table 9.1. CIP-51 Instruction Set Summary (Continued)

Mnemonic

Description

Bytes

Clock

Cycles

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