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C8051F360 Datasheet(PDF) 36 Page - Silicon Laboratories

Part # C8051F360
Description  Mixed Signal ISP Flash MCU Family
PDF  288 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F360 Datasheet(HTML) 36 Page - Silicon Laboratories

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C8051F360/1/2/3/4/5/6/7/8/9
36
Rev. 1.0
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F36x
Name
Pin
‘F360/3
(48-pin)
Pin
‘F361/4/6/8
(32-pin)
Pin
‘F362/5/7/9
(28-pin)
Type
Description
VDD 19, 31, 43
4
4
Power Supply Voltage.
GND 18, 30, 42
3
3
Ground.
AGND
6
—
—
Analog Ground.
AV+
7
—
—
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
RST/
C2CK
8
5
5
D I/O
D I/O
Device Reset. Open-drain output of internal POR or
VDD Monitor. An external source can initiate a system
reset by driving this pin low for at least 10 µs.
Clock signal for the C2 Debug Interface.
P4.6/
C2D
9
—
—
D I/O or
A In
D I/O
Port 4.6. See Section 17 for a complete description.
Bi-directional data signal for the C2 Debug Interface.
P3.0/
C2D
—
6
6
D I/O or
A In
D I/O
Port 3.0. See Section 17 for a complete description.
Bi-directional data signal for the C2 Debug Interface.
P0.0
5
2
2
D I/O or
A In
Port 0.0. See Section 17 for a complete description.
P0.1
4
1
1
D I/O or
A In
Port 0.1. See Section 17 for a complete description.
P0.2
3
32
28
D I/O or
A In
Port 0.2. See Section 17 for a complete description.
P0.3
2
31
27
D I/O or
A In
Port 0.3. See Section 17 for a complete description.
P0.4
1
30
26
D I/O or
A In
Port 0.4. See Section 17 for a complete description.
P0.5
48
29
25
D I/O or
A In
Port 0.5. See Section 17 for a complete description.
P0.6
47
28
24
D I/O or
A In
Port 0.6. See Section 17 for a complete description.
P0.7
46
27
23
D I/O or
A In
Port 0.7. See Section 17 for a complete description.



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