C8051F360 datasheet(81/288 Pages) SILABS

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DATA BUS

TMP1

TMP2

PRGM. ADDRESS REG.

PC INCREMENTER

ALU

PSW

DATA BUS

MEMORY

INTERFACE

MEM_ADDRESS

PIPELINE

BUFFER

DATA POINTER

INTERRUPT

INTERFACE

SYSTEM_IRQs

EMULATION_IRQ

MEM_CONTROL

CONTROL

LOGIC

A16

PROGRAM COUNTER (PC)

STOP

CLOCK

RESET

IDLE

POWER CONTROL

SFR

BUS

INTERFACE

SFR_ADDRESS

SFR_CONTROL

SFR_WRITE_DATA

SFR_READ_DATA

B REGISTER

ACCUMULATOR

MEM_WRITE_DATA

MEM_READ_DATA

SRAM

ADDRESS

SRAM

(256 X 8)

STACK POINTER

Rev. 1.0

C8051F360/1/2/3/4/5/6/7/8/9

Figure 9.1. CIP-51 Block Diagram

9.2.

Programming and Debugging Support

A C2-based serial interface is provided for in-system programming of the Flash program memory and com-

munication with on-chip debug support logic. The re-programmable Flash can also be read and changed

by the application software using the MOVC and MOVX instructions. This feature allows program memory

to be used for non-volatile data storage as well as updating program code under software control.

The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware

breakpoints and watch points, starting, stopping and single stepping through program execution (including

interrupt service routines), examination of the program's call stack, and reading/writing the contents of reg-

isters and memory. This method of on-chip debug is completely non-intrusive and non-invasive, requiring

no RAM, Stack, timers, or other on-chip resources.

The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-

vides an integrated development environment (IDE) including editor, macro assembler, debugger and pro-

grammer. The IDE's debugger and programmer interface to the CIP-51 via its C2 interface to provide fast

and efficient in-system device programming and debugging. Third party macro assemblers and C compil-

ers are also available.

C8051F360 Datasheet(PDF) 81 Page - Silicon Laboratories

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