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KS8893ML Datasheet(PDF) 53 Page - Micrel Semiconductor

Part # KS8893ML
Description  Integrated 3-Port 10/100 Managed Switch with PHYs Preliminary Data Sheet Rev. 1.0
PDF  106 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

KS8893ML Datasheet(HTML) 53 Page - Micrel Semiconductor

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Micrel
KS8893M/ML/MI
June 2005
53
M9999-063005
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status
Bit
Name
R/W
Description
Default
Reference
15
Vct_enable
R/W
(SC)
1 = enable cable diagnostic. After VCT test
has completed, this bit will be self-cleared.
0 = indicate cable diagnostic test (if
enabled) has completed and the status
information is valid for read.
0
Reg. 26, bit 4
Reg. 42, bit 4
14-13
Vct_result
RO
00 = normal condition
01 = open condition detected in cable
10 = short condition detected in cable
11 = cable diagnostic test has failed
00
Reg 26, bit[6:5]
Reg 42, bit[6:5]
12
Vct 10M Short
RO
1 = Less than 10 meter short
0
Reg. 26, bit 7
Reg. 42, bit 7
11-9
Reserved
RO
Reserved
000
8-0
Vct_fault_count
RO
Distance to the fault.
It’s approximately 0.4m*vct_fault_count[8:0]
{0, (0x00)}
{(Reg. 26, bit
0), (Reg. 27,
bit[7:0])}
{(Reg. 42, bit
0), (Reg. 43,
bit[7:0])}
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status
Bit
Name
R/W
Description
Default
Reference
15-6
Reserved
RO
Reserved
{(0x00),00}
5
Polrvs
RO
1 = polarity is reversed
0 = polarity is not reversed
0
Reg. 31, bit 5
Reg. 47, bit 5
4
MDI-X status
RO
1 = MDI-X
0 = MDI
0
Reg. 30, bit 7
Reg. 46, bit 7
3
Force_lnk
R/W
1 = Force link pass
0 = Normal Operation
0
Reg. 26, bit 3
Reg. 42, bit 3
2
Pwrsave
R/W
1 = Enable power saving
0 = Disable power saving
1
Reg. 26, bit 2
Reg. 42, bit 2
1
Remote
Loopback
R/W
1 = Perform Remote loopback, as follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Port 2 (reg. 42, bit 1 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 2’s PHY
End: TXP2/TXM2 (port 2)
0 = Normal Operation
0
Reg. 26, bit 1
Reg. 42, bit 1
0
Reserved
R/W
Reserved
Do not change the default value.
0



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