KS8893ML datasheet(22/106 Pages) MICREL

22 / 106 page

Micrel

KS8893M/ML/MI

June 2005

M9999-063005

PLL Clock Synthesizer

The KS8893M generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are

generated from an external 25MHz crystal or oscillator. In RMII mode, these internal clocks are generated from

an external 50MHz oscillator or system clock.

Scrambler/De-scrambler (100BASE-TX Only)

The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic

interference (EMI) and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear

feedback shift register (LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver

then de-scrambles the incoming data stream using the same sequence as at the transmitter.

100BASE-FX Operation

100BASE-FX operation is similar to 100BASE-TX operation with the differences being that the scrambler/de-

scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto negotiation

is bypassed and auto MDI/MDI-X is disabled.

100BASE-FX Signal Detection

In 100BASE-FX operation, FXSD1 (fiber signal detect), input pin 44, is usually connected to the fiber transceiver

SD (signal detect) output pin. 100BASE-FX mode is activated when the FXSD1 input pin is greater than 1V.

When FXSD1 is between 1V and 1.8V, no fiber signal is detected and a far-end fault (FEF) is generated. When

FXSD1 is over 2.2V, the fiber signal is detected.

Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1 input pin is tied

high to force 100BASE-FX mode.

100BASE-FX signal detection is summarized in the following table:

FXSD1 Input Voltage

Mode

Less than 0.2V

TX mode

Greater than 1V, but less than 1.8V

FX mode

No signal detected.

Far-end fault generated

Greater than 2.2V

FX mode

Signal detected

Table 1. FX and TX Mode Selection

To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output

voltage swing to match the FXSD1 pin’s input voltage threshold.

100BASE-FX Far-End Fault

A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver.

The KS8893M detects a FEF when its FXSD1 input is between 1V and 1.8V. When a FEF is detected, the

KS8893M signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle

period between frames.

By default, FEF is enabled. FEF can be disabled through register setting.

KS8893ML Datasheet(PDF) 22 Page - Micrel Semiconductor

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