KS8893ML datasheet(36/106 Pages) MICREL

36 / 106 page

Micrel

KS8893M/ML/MI

June 2005

M9999-063005

Serial Management Interface (SMI)

The SMI is the KS8893M non-standard MIIM interface that provides access to all KS8893M configuration

registers. This interface allows an external device to completely monitor and control the states of the KS8893M.

The SMI interface consists of the following:

A physical connection that incorporates the data line (MDIO) and the clock line (MDC).

A specific protocol that operates across the aforementioned physical connection that allows an external

controller to communicate with the KS8893M device.

Access to all KS8893M configuration registers. Register access includes the Global, Port and

Advanced Control Registers 0-141 (0x00 – 0x8D), and indirect access to the standard MIIM registers

[0:5] and custom MIIM registers [29, 31].

The following table depicts the SMI frame format.

Preamble

Start of

Frame

Read/Write

OP Code

PHY

Address

Bits [4:0]

REG

Address

Bits [4:0]

Data

Bits [15:0]

Idle

Read

32 1’s

1xRRR

RRRRR

0000_0000_DDDD_DDDD

Write

32 1’s

0xRRR

RRRRR

xxxx_xxxx_DDDD_DDDD

Table 8. Serial Management Interface (SMI) Frame Format

SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI

address bit[3] is undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write

operations.

To access the KS8893M registers 0-141 (0x00 – 0x8D), the following applies:

PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address;

that is, {PHYAD[2:0], REGAD[4:0]} = bits [7:0] of the 8-bit address.

Registers are 8 data bits wide.

For read operation, data bits [15:8] are read back as 0’s.

For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.

SMI register access is the same as the MIIM register access, except for the register access requirements

presented in this section.

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