KS8893ML datasheet(21/106 Pages) MICREL

21 / 106 page

Micrel

KS8893M/ML/MI

June 2005

M9999-063005

Functional Description

The KS8893M contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer 2

managed switch.

The KS8893M has the flexibility to reside in either a managed or unmanaged design. In a managed design, the

host processor has complete control of the KS8893M via the SMI interface, MIIM interface, SPI bus, or I

2C bus.

An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.

On the media side, the KS8893M supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports, and also

100BASE-FX on PHY port 1, which allows the KS8893M to be used as a media converter.

The KS8893ML is the single supply version with all the identical rich features of the KS8893M. In the KS8893ML

version, pin number 22 provides 1.2V output power to the KS8893ML’s VDDC, VDDA, and VDDAP power pins. Refer

to the Pin Description table for information about pin 22 (Pin Description and I/0 Assignment).

Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make

the design more efficient and allow for lower power consumption and smaller chip die size.

Functional Overview: Physical Layer Transceiver

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-

NRZI conversion, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz

serial bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The

serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The

output current is set by an external1% 3.01K

Ω resistor for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding

amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the

100BASE-TX transmitter.

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion,

data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel

conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the

twisted pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer

must adjust its characteristics to optimize performance. In this design, the variable equalizer makes an initial

estimation based on comparisons of incoming signal strength against some known cable characteristics, and then

tunes itself for optimization. This is an ongoing process and self-adjusts against environmental changes such as

temperature variations.

Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is

used to compensate for the effect of baseline wander and to improve the dynamic range. The differential data

conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is

then used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed

by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to

the MAC.

KS8893ML Datasheet(PDF) 21 Page - Micrel Semiconductor

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