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KS8893ML Datasheet(PDF) 82 Page - Micrel Semiconductor

Part # KS8893ML
Description  Integrated 3-Port 10/100 Managed Switch with PHYs Preliminary Data Sheet Rev. 1.0
PDF  106 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

KS8893ML Datasheet(HTML) 82 Page - Micrel Semiconductor

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Micrel
KS8893M/ML/MI
June 2005
82
M9999-063005
Register 111 (0x6F): TOS Priority Control Register 15
Bit
Name
R/W
Description
Default
7-6
DSCP[127:126]
R/W
The value in this field is used as the frame’s
priority when bits [7:2] of the frame’s IP
TOS/DiffServ/Traffic Class value is 0xFC.
00
5-4
DSCP[125:124]
R/W
The value in this field is used as the frame’s
priority when bits [7:2] of the frame’s IP
TOS/DiffServ/Traffic Class value is 0xF8.
00
3-2
DSCP[123:122]
R/W
The value in this field is used as the frame’s
priority when bits [7:2] of the frame’s IP
TOS/DiffServ/Traffic Class value is 0xF4.
00
1-0
DSCP[121:120]
R/W
The value in this field is used as the frame’s
priority when bits [7:2] of the frame’s IP
TOS/DiffServ/Traffic Class value is 0xF0.
00
Registers 112 to 117
Registers 112 to 117 contain the switch engine’s MAC address. This 48-bit address is used as the Source
Address for the MAC’s full duplex flow control (PAUSE) frame.
Register 112 (0x70): MAC Address Register 0
Bit
Name
R/W
Description
Default
7-0
MACA[47:40]
R/W
0x00
Register 113 (0x71): MAC Address Register 1
Bit
Name
R/W
Description
Default
7-0
MACA[39:32]
R/W
0x10
Register 114 (0x72): MAC Address Register 2
Bit
Name
R/W
Description
Default
7-0
MACA[31:24]
R/W
0xA1
Register 115 (0x73): MAC Address Register 3
Bit
Name
R/W
Description
Default
7-0
MACA[23:16]
R/W
0xFF
Register 116 (0x74): MAC Address Register 4
Bit
Name
R/W
Description
Default
7-0
MACA[15:8]
R/W
0xFF
Register 117 (0x75): MAC Address Register 5
Bit
Name
R/W
Description
Default
7-0
MACA[7:0]
R/W
0xFF



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