TLC6989 datasheet(16/72 Pages) TI1

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7.3.4.4 SPI Communications Error

7.3.4.4.1 Reset Timer

The TLC6989 monitors the SPI for communication with an internal SPI reset timer. Once an SPI command is

started, the timer starts and the device expects the full command (including reading of data) is completed before

the timer overflows. The timer starts counting from the first clock pulse on the SCLK pin (with CS pin at active

state) when the device is trying to detect the SPI command word. The timer is reset when the device starts to

wait for the next SPI command word. If the watchdog timer overflows, the SPI peripheral is reset and starts to

wait to receive the next SPI command word. In addition, the FLAG_SPI_TIMEOUT, FLAG_SPI, and FLAG_ERR

are set to 1. The SPI controller can access the TLC6989 and write 1 to CLR_FLAG to clear the flags. The SPI

reset timer is programmable by 4-bit field SPI_RST_TIMEOUT_CFG in register SPICTRL. TI recommends to

enable this timer when the CS pin is always tied to the active state.

7.3.4.4.2 Chip Select (CS) Reset

The SPI peripheral is reset by pulling the CS pin to logic HIGH. This is normally done when the whole SPI

command has been completed and the SPI peripheral is waiting for the next command. In case the CS pin

is pulled high after the SPI peripheral has received the SPI command word, but before the whole command

is received, the FLAG_SPI_CS, FLAG_SPI, and FLAG_ERR are set to 1. The SPI controller can access the

TLC6989 and write 1 to CLR_FLAG to clear the flags.

7.3.4.4.3 CRC Error

The CRC word is the final word of a command the SPI controller transmits to make sure the TLC6989 correctly

has received all the words from SPI controller. The SPI controller must calculate the CRC value for all words

including SPI command word and any data words. The TLC6989 receives all words, calculates the CRC

word and compares the calculated CRC word with received CRC word. If two CRC words do not match, the

TLC6989 sets FLAG_SPI_CRC and FLAG_ERR to 1. Dependent on the received command, the TLC6989

ignores the command or continues processing the command. The SPI controller can access the device and

write 1 to CLR_FLAG to clear the flags. Two different CRC algorithms are supported. The default algorithm is

CCITT-FALSE. This can be changed to the CRC-16/XMODEM algorithm using the REG_WR SPI command.

After changing the CRC algorithm, the next SPI command uses the new algorithm.

7.3.4.4.4 Register write failure

The CCSICTRL register is prohibted to be written while the CCSI controller is transmitting or CCSI peripheral

is receiving. In that way the continuous clock output on CLK_O remains aligned with the data being transmitted

on SOUT and received on SIN. When the user tries to write the CCSICTRL register during CCSI controller

and/or peripheral activity, the device automatically detects this and sets FLAG_SPI_REG_WRITE to 1. The SPI

controller can access the device and write 1 to CLR_FLAG to clear the flag.

7.3.4.5 CCSI Communications Loss

7.3.4.5.1 SIN Stuck-at Diagnostics

The data input (SIN) pin of the CCSI peripheral is monitored. After the CCSI controller starts transmitting (logic

high to low transition on SOUT pin), the timer starts counting. If no toggling has been detected on the SIN pin

before the timer overflows (after 5 milliseconds), the FLAG_CCSI_SIN, FLAG_CCSI, and FLAG_ERR are set to

1. The SPI controller can access the TLC6989 and write 1 to CLR_FLAG to clear the flags.

When the FLAG_CCSI_SIN is set, the CCSI controller and CCSI peripheral are likely to get out of

synchronization. Therefore, TI recommends to perform a SOFTRESET command after this flag has been set.

7.3.4.6 CCSI Communications Error

The CCSI peripheral diagnoses the received data. The check bit detection is checked on all received data while

the data integrity is only checked for CCSI commands that did not add or modify data which was transmitted by

the CCSI controller.

TLC6989

SLVSHF5 – NOVEMBER 2024

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