TLC6989 datasheet(14/72 Pages) TI1

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7.3.3.1 FIFO level and Data Ready (DRDY) Interrupt

The TXFIFO level (TXFFLVL) controls the start of the transmission of the CCSI controller for SPI forward

commands that are independent of the SPI CRC. With correct setting of the FIFO level, FIFO overflow and

underflow can be prevented. The setting is dependent on the difference between the SPI clock frequency and

CCSI clock frequency, the accuracy of the clock provided to the SPI peripheral, accuracy of the clock of the

CCSI controller, and the maximum length of data that is being forwarded.

The RXFIFO level (RXFFLVL) controls the Data Ready (DRDY) interrupt. When the number of data words on the

RXFIFO exceed the RXFFLVL, the DRDY pin becomes logic LOW. This DRDY pin remains logic LOW until there

are no more words on the RXFIFO. The RXFFLVL setting has the same dependencies as the TXFFLVL except

the maximum length of data that is being forwarded is replaced by the maximum number of data words that is

received by the CCSI peripheral. An example of the DRDY pin's behavior is depicted in Figure 7-7.

SIN

RXFFST

Data0

Data1

Data2

Data3

DRDY

END

SDO

Data0

Data1

Data2

Data3

CRC

DATA RD

SDI

CRC

Figure 7-7. Example of DRDY pin with RXFFLVL register set to 3

The DRDY pin also becomes logic LOW when an END byte is detected and the number of words on the RXFIFO

has not reached the RXFFLVL yet.

7.3.3.2 FIFO Clearance

To stop an ongoing CCSI transmission, the TXFIFO can be cleared by bit TXFFCLR in register TXFFLVL. This

resets the TXFIFO counter (TXFFST) to 0. All the commands in the queue are cleared. The CCSI controller

automatically inserts an END byte to reset the LED drivers. The CCSI peripheral continues to work as normal.

The TXFFCLR bit automatically returns to 0.

The data on the RXFIFO can be cleared by bit RXFFCLR in register RXFFLVL. This resets the RXFIFO counter

(RXFFST) to 0. If the CCSI peripheral is receiving data that needs to be stored on the RXFIFO, the storage is

stopped for this command. The next CCSI command received by the CCSI peripheral follows the original request

of the SPI command. The CCSI controller continues to work as normal. The RXFFCLR bit automatically returns

to 0.

TLC6989

SLVSHF5 – NOVEMBER 2024

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