TLC6989 datasheet(13/72 Pages) TI1

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7.3.3 FIFO

The TLC6989 has both a transmit and receive FIFO. The naming of the FIFOs are viewed from the Continuous

Clock Serial Interface (CCSI). That means the transmit FIFO (TXFIFO) is the data that was received by the SPI

peripheral and transmitted by the CCSI controller. The receive FIFO (RXFIFO) is the data received by the CCSI

peripheral which can be read by the controller via SPI peripheral.

Both FIFOs are 16-bit-wide first-in-first-out memory buffers. The FIFOs are used to store data words to fullfil

the timing requirements while the data is crossing between the SPI clock domain and CCSI clock domain. The

TXFIFO holds the data during the crossover from the SPI clock to the CCSI clock domain. The RXFIFO holds

the data during the crossover from the CCSI clock domain to the SPI clock domain.

When the SPI clock domain runs at a higher frequency than the CCSI clock domain, the TXFIFO stores data

already received by the SPI peripheral which has not been transmitted yet by the CCSI controller. A counter

(TXFFST) keeps track of the number of words currently stored in the TXFIFO. The example where the SPI

peripheral runs at a higher clock frequency than the CCSI controller is depicted in Figure 7-5. Note that in this

figure every data word is 16 bits. That means that when the width of the block is larger, the clock frequency is

lower.

SPI CMD

SDI

TXFFST

Data0

Data1

Data2

Data3

Data1

Data2

Data3

SOUT

Data0

CRC

Figure 7-5. Example of SPI peripheral running at higher frequency than CCSI controller

When the SPI peripheral runs at a lower clock frequency than the CCSI controller, the TXFIFO is used to first

store a number of data words received by the SPI peripheral before the transmission by the CCSI controller

starts. Following this method, the data stream on the CCSI can be made continuous without requiring the

continuous clock to stop because the data word was not received yet by the SPI peripheral. An example of this

situation is depicted in Figure 7-6.

SDI

TXFFST

SPI CMD

Data0

Data1

Data2

Data3

Data1

Data2

Data3

SOUT

Data0

CRC

Figure 7-6. Example of SPI peripheral running at lower frequency than CCSI controller

For the RXFIFO, the CCSI peripheral receives the data and stores them on the RXFIFO. The SPI peripheral

reads the data from the RXFIFO and transmits them to the SPI controller. Also for the RXFIFO a counter

(RXFFST) exists to keep track of the number of data words currently stored.

Note that when an END byte is received, the storage stops. The END byte itself is not stored on the RXFIFO.

Also the START bit and CHECK bits are not stored.

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TLC6989

SLVSHF5 – NOVEMBER 2024

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