TLC6989 datasheet(6/72 Pages) TI1

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6.6 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

fSCLK,NORMAL

SCLK clock frequency in NORMAL state

MHz

fSCLK,INIT

SCLK clock frequency in INIT state

MHz

tLEAD,CS

Delay time, first SCLK rising edge after CS

falling edge

tLAG,CS

Delay time, CS rising edge after final SCLK

falling edge

tSU,SDI

SDI input data setup time before SCLK rising

egde

tHD,SDI

SDI input data hold time after SCLK rising

edge

twh,CS

Pulse duration, CS high

tSU,SIN

SIN input data setup time before CLK_O rising

and falling edge

tHD,SIN

SIN input data hold time after CLK_O rising

and falling edge

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tACC,CS

Propagation delay time, CS falling edge to

SDO driven

tDIS,CS

Propagation delay time, CS rising edge to

SDO high impedance

tVALID,SDO

Propagation delay time, SCLK falling edge to

valid new SDO

tr,SOUT

Rise time (SOUT) - from 10% of VCC to 90%

of VCC

VCC = 3.3V, CSOUT = 30pF

tf,SOUT

Fall time (SOUT) - from 90% of VCC to 10% of

VCC

VCC = 3.3V, CSOUT = 30pF

fCLK_O

CLK_O output frequency. The output voltage

reaches at least 10% and 90% VCC at the

specified toggle frequency.

VCC = 3.3V, CCLK_O = 30pF

10.3

MHz

TLC6989

SLVSHF5 – NOVEMBER 2024

www.ti.com

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