| Electronic Components Datasheet Search |
|
TLC6989 Datasheet(PDF) 11 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TLC6989 Datasheet(HTML) 11 Page - Texas Instruments |
|
11 / 72 page ![]() 7.3.2.1 Command Format The command format is viewed from the CCSI peripheral side. Figure 7-2 defines the format of the command transmission. There are three states in one command: • IDLE: CLK_O is always active and continuous. SIN is always HIGH. • START: SIN changes from HIGH to LOW after the IDLE state. • DATA: – Head_byte: The command identifier, contains one 16-bit data and one check bit. – Data_bytes_N-1: Each data-byte contains 3 × 17-bit data, each 17-bit data contains one 16-bit data word and one check bit. • END: The device recognizes continuous 18-bit HIGH on SIN, and then returns to IDLE state. • CHECK BIT: The check bit (17th bit) value is the NOT of 16th bit value to avoid continuous 18-bit HIGH (to distinguish with END). The IDLE state is not necessary, which means the START state of the next command can connect to the END state of the current command. Head_byte Data_bytes_N End_bytes Data_bytes_1 CLK_O SIN …... IDLE START DATA END IDLE Figure 7-2. Command Format 7.3.2.2 Command Recognition and Synchronization Two different CCSI commands require at least one END byte in between the commands to be able to be recognized as separate commands. The TLC6989 automatically inserts one END byte after all the data from one SPI command has been transmitted. However, for certain CCSI commands, the LED drivers add data to the data stream. In this case, one END byte during transmission is not sufficient to distinguish the two CCSI commands by the CCSI peripheral. Without sufficient END bytes, the CCSI controller and CCSI peripheral get out of synchronization. The synchronization is required for several actions. For example, to determine if the received data needs to be stored on the RXFIFO or if a CRC needs to be calculated over the received data and compared to the CRC over the transmitted data. In case the synchronization is lost, the SPI command SOFTRESET_CRC can be used to bring the CCSI controller and peripheral back in sync. The SPI controller is responsible there are sufficient END bytes between CCSI commands to keep the synchronization by using a dedicated SPI command that inserts extra END bytes. 7.3.2.3 CCSI Command Queue The CCSI controller has the ability to queue multiple SPI commands. This means that when the CCSI controller is still transmitting, a new SPI forward command can be received by the SPI peripheral. This new command is automatically transmitted after the old command is finished transmitting. An example is depicted in Figure 7-3. Note that in this figure every data word is 16 bits. That means that when the width of the block is larger, the clock frequency is lower. In this example the CCSI frequency is lower than the SPI frequency. SDI SDO SOUT SPI CMD Data0 Data1 Data2 CRC0 STATUS CRC1 Data0 END SPI CMD Data3 CRC2 Data1 Data2 STATUS CRC1 Data3 END Figure 7-3. Example of queuing CCSI commands www.ti.com TLC6989 SLVSHF5 – NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLC6989 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |