TLC6989 datasheet(18/72 Pages) TI1

18 / 72 page

TLC6989 and write 1 to CLR_FLAG to clear the flags. The error flag has to be cleared to be able to store new

CCSI data words on the TXFIFO and the CCSI controller can start transmitting.

7.3.4.7.4 RXFIFO Overflow

When the RXFIFO is full (RXFFST = 0x0FF) and new data words are received by the CCSI peripheral which

have to be stored in the RXFIFO, the FLAG_RXFFOVF, FLAG_RXFF, and FLAG_ERR are set to 1. The RXFIFO

is not cleared and data can still be accessed by the SPI controller. The SPI controller can access the TLC6989

and write 1 to CLR_FLAG to clear the flags. The CCSI peripheral can only start storing new data in the

RXFIFO after the error flag is cleared. The storage starts from the first CCSI head_byte that is received from a

FWD_RD_END or FWD_RD_END_CRC SPI command.

7.3.4.7.5 RXFIFO Underflow

When the RXFIFO is empty (RXFFST = 0x0) and the SPI peripheral tries to read new data words from the

RXFIFO, the FLAG_RXFFUVF, FLAG_RXFF, and FLAG_ERR are set to 1. The SPI controller can access the

TLC6989 and write 1 to CLR_FLAG to clear the flags. The CCSI peripheral can only start storing new data in the

RXFIFO after the error flag is cleared. The storage starts from the first CCSI head_byte that is received from a

FWD_RD_END or FWD_RD_END_CRC SPI command.

7.3.4.7.6 RXFIFO Single Error Detection (SED)

The RXFIFO is protected with a parity bit. When a single bit error is detected during a read operation from the

RXFIFO, the FLAG_RXFFSED, FLAG_RXFF, and FLAG_ERR are set to 1. The SPI controller can access the

TLC6989 and write 1 to CLR_FLAG to clear the flags.

7.3.4.8 OTP CRC Error

The internal OTP is protected by an 8-bit CRC based on the polynomial X8 + X2 + X + 1. When the device

powers up, the OTP is read and the read CRC is compared to the calculated CRC of all the read OTP bytes.

When the CRC does not match, the FLAG_OTP_CRC and FLAG_ERR are set to 1. This flag cannot be cleared

by the SPI controller. The device remains in Initialization state. Only powering down and up VCC can restart the

reading of the OTP.

TLC6989

SLVSHF5 – NOVEMBER 2024

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TLC6989 Datasheet(PDF) 18 Page - Texas Instruments