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TLC6989 Datasheet(PDF) 35 Page - Texas Instruments |
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TLC6989 Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 72 page ![]() 7.6.2 SPICTRL Register (Address = 0x1) [Reset = 0x00A0] SPICTRL is shown in Figure 7-24 and described in Table 7-6. Return to the DEVICE Registers Summary Table. Figure 7-24. SPICTRL Register 15 14 13 12 11 10 9 8 RESERVED SPI_WDT_CFG RESERVED R/W-0x0 R/W-0x0 R/W-0x0 7 6 5 4 3 2 1 0 SPI_RST_TIMEOUT_CFG RESERVED SPI_CRC_ALG SPI_SDO_DIS SPI_ACK_DIS R/W-0xA R/W-0x0 R/W-0x0 R/W-0x0 R/W-0x0 Table 7-6. SPICTRL Register Field Descriptions Bit Field Type Reset Description 15-14 RESERVED R/W 0x0 Reserved 13-12 SPI_WDT_CFG R/W 0x0 Watchdog on SPI to into FAILSAFE state 0x0 = 40ms 0x1 = 20ms 0x2 = 10ms 0x3 = Disabled 11-8 RESERVED R/W 0x0 Reserved 7-4 SPI_RST_TIMEOUT_CFG R/W 0xA Watchdog on SCLK to reset SPI after timeout 0x0 = Disabled 0x1 = 500us 0x2 = 1ms 0x3 = 2ms 0x4 = 3ms 0x5 = 4ms 0x6 = 5ms 0x7 = 10ms 0x8 = 15ms 0x9 = 20ms 0xA = 30ms 0xB = 40ms 0xC = 50ms 0xD = 85ms 0xE = 100ms 0xF = 200ms 3 RESERVED R/W 0x0 Reserved 2 SPI_CRC_ALG R/W 0x0 CRC algorithm used for SPI communication 0x0 = CCITT-FALSE is used 0x1 = CRC-16/XMODEM is used 1 SPI_SDO_DIS R/W 0x0 Disable bit for SPI SDO 0x0 = SDO is driven when CS is low 0x1 = SDO is always High Impedance 0 SPI_ACK_DIS R/W 0x0 Disable bit for SPI auto-reply of STATUS register 0x0 = Auto-reply is enabled 0x1 = Auto-reply is disabled www.ti.com TLC6989 SLVSHF5 – NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TLC6989 |
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