TMPR4937 datasheet(373/552 Pages) TOSHIBA

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Chapter 11 Serial I/O Port

11-13

11.4.1 Line Control Register 0 (SILCR0)

0xF300 (Ch. 0)

Line Control Register 1 (SILCR1)

0xF400 (Ch. 1)

These registers specify the format of asynchronous transmission/reception data.

Reserved

: Type

: Initial value

R/WUB TWUB UODE

Reserved

SCS

UEPS UPEN USBL

UMODE

R/W

: Type

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:16

Reserved

⎯

RWUB

Receive Wake

Up Bit

Wake Up Bit for Receive (Default: 0)

When in the Multi-Controller System mode, this field selects whether to

receive address (ID) frames whose Wake Up bits (WUB) are “1” or to

receive data frames whose Wake Up bits (WUB) are “0”. This value is

undefined when not in the Multi-Controller System mode.

0: Receive data frames.

1: Receive address (ID) frames.

R/W

TWUB

Transmit Wake

Up Bit

Wake Up Bit for Transmit (Default: 1)

When in the Multi-Controller System mode, this field specifies the Wake Up

bit (WUB). This value is undefined when not in the Multi-Controller System

mode.

0: Data frame transfer (WUB = 0)

1: Address (ID) frame transfer (WUB = 1)

R/W

UODE

Open Drain

Enable

TXD Open Drain Enable (Default: 0)

This field selects the output mode of the TXD signal. When in the Multi-

Controller System mode, the Slave Controller must set the TXD signal to

Open Drain.

0: Totem pole output

1: Open drain output

R/W

12:7

Reserved

⎯

6:5

SCS

Clock Select

SIO Clock Select (Default: 00)

This field selects the serial transfer clock. The clock frequency that is the

serial transfer clock divided by 16 becomes the baud rate (bps).

00: Internal clock (IMBUSCLK)

01: Baud rate generator output that divided IMBUSCLK

10: External clock (SCLK)

11: Baud rate generator output that divided SCLK

R/W

UEPS

Even Parity

Select

UART Even Parity Select (Default: 0)

This field selects the parity mode.

0: Odd parity

1: Even parity

R/W

UPEN

Parity Check

Enable

UART Parity Enable (Default: 0)

This field selects whether to perform the parity check. This bit must be

cleared in multidrop systems (i.e., when the UMODE field is 10 or 11.)

0: Disable the parity check

1: Enable the parity check

R/W

Figure 11.4.1 Line Control Register (1/2)

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