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TMPR4937 Datasheet(PDF) 399 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 399 Page - Toshiba Semiconductor |
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399 / 552 page ![]() Chapter 12 Timer/Counter 12-15 12.4.6 Divide Register n (TMCCDRn) TMCCDR0 0xF020 TMCCDR1 0xF120 TMCCDR2 0xF220 31 16 Reserved : Type : Initial value 15 3 2 0 Reserved CCD R/W : Type 000 : Initial value Bits Mnemonic Field Name Description Read/Write 31:3 Reserved ⎯ 2:0 CCD Counter Clock Divide Value Counter Clock Divide (Default: 000) These bits specify the divide value when using the internal clock (IMBUSCLK) as the counter input clock source. The binary value n is divided by 2n+1. 000: Divide by 21 (f/2) 001: Divide by 22 (f/4) 010: Divide by 23 (f/8) 011: Divide by 24 (f/16) 100: Divide by 25 (f/32) 101: Divide by 26 (f/64) 110: Divide by 27 (f/128) 111: Divide by 28 (f/256) R/W Figure 12.4.6 Divide Register |
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