TMPR4937 datasheet(467/552 Pages) TOSHIBA

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Chapter 15 Interrupt Controller

15-21

15.4.6 Interrupt Level Register 2 (IRLVL2)

0xF618

Reserved

IL21

Reserved

: Type

: Default

Reserved

IL5

Reserved

IL4

R/W

: Type

000

: Default

Bit

Mnemonic

Field Name

Explanation

Read/Write

31:27

⎯

Reserved

⎯

26:24

IL21

Interrupt Level 21

Interrupt Level of INT [21] (Default: 000)

These bits specify the interrupt level of NDFMC.

000: Interrupt level 0 (Interrupt disable)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

23:11

⎯

Reserved

⎯

10:8

IL5

Interrupt Level 5

Interrupt Level of INT [5] (Default: 000)

These bits specify the interrupt level of external INT[3] / ETHERC1.

000: Interrupt level 0 (Interrupt disable)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

7:3

⎯

Reserved

⎯

2:0

IL4

Interrupt Level 4

Interrupt Level of INT [4] (Default: 000)

These bits specify the interrupt level of external INT[2].

000: Interrupt level 0 (Interrupt disable)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

Figure 15.4.6 Interrupt Level Register 2

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