TMPR4937 datasheet(470/552 Pages) TOSHIBA

470 / 552 page

Chapter 15 Interrupt Controller

15-24

15.4.8 Interrupt Level Register 4 (IRLVL4)

0xF620

Reserved

IL25

Reserved

IL24

R/W

: Type

000

: Default

Reserved

IL9

Reserved

IL8

R/W

: Type

000

: Default

Bit

Mnemonic

Field Name

Explanation

Read/Write

31:27

⎯

Reserved

⎯

26:24

IL25

Interrupt level 25

Interrupt Level of INT [25] (Default: 000, R/W)

These bits specify the interrupt level of ACLCPME interrupts.

000: Interrupt level 0 (Interrupt disabled)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

23:19

⎯

Reserved

⎯

18:16

IL24

Interrupt level 24

Interrupt Level of INT [24] (Default: 000, R/W)

These bits specify the interrupt level of ACLC interrupts.

000: Interrupt level 0 (Interrupt disabled)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

15:11

⎯

Reserved

⎯

10:8

IL9

Interrupt level 9

Interrupt Level of INT [9] (Default: 000)

These bits specify the interrupt level of SIO [1] interrupts.

000: Interrupt level 0 (Interrupt disabled)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

7:3

⎯

Reserved

⎯

Figure 15.4.8 Interrupt Level Register 4 (1/2)

TMPR4937 Datasheet(PDF) 470 Page - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 470 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL