TMPR4937 datasheet(472/552 Pages) TOSHIBA

472 / 552 page

Chapter 15 Interrupt Controller

15-26

15.4.9 Interrupt Level Register 5 (IRLVL5)

0xF624

Reserved

IL27

Reserved

IL26

R/W

: Type

000

: Default

Reserved

IL11

Reserved

IL10

R/W

: Type

000

: Default

Bit

Mnemonic

Field Name

Explanation

Read/Write

31:27

⎯

Reserved

⎯

26:24

IL27

Interrupt level 27

Interrupt Level of INT [27] (Default: 000)

These bits specify the interrupt level of DMA1 [0] interrupts.

000: Interrupt level 0 (Interrupt disabled)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

23:19

⎯

Reserved

⎯

18:16

IL26

Interrupt level 26

Interrupt Level of INT [26] (Default: 000)

These bits specify the interrupt level of PCIC1 interrupts.

000: Interrupt level 0 (Interrupt disabled)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

15:11

⎯

Reserved

⎯

10:8

IL11

Interrupt level 11

Interrupt Level of INT [11] (Default: 000)

These bits specify the interrupt level of DMA0 [1] interrupts.

000: Interrupt level 0 (Interrupt disabled)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

7:3

⎯

Reserved

⎯

Figure 15.4.9 Interrupt Level Register 5 (1/2)

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