TMPR4937 datasheet(468/552 Pages) TOSHIBA

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Chapter 15 Interrupt Controller

15-22

15.4.7 Interrupt Level Register 3 (IRLVL3)

0xF61C

Reserved

IL23

Reserved

IL22

R/W

: Type

000

: Default

Reserved

IL7

Reserved

IL6

R/W

: Type

000

: Default

Bit

Mnemonic

Field Name

Explanation

Read/Write

31:27

⎯

Reserved

⎯

26:24

IL23

Interrupt Level 23

Interrupt Level of INT [23] (Default: 000)

These bits specify the interrupt level of PCIPME0 interrupts.

000: Interrupt level 0 (Interrupt disabled)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

23:19

⎯

Reserved

⎯

18:16

IL22

Interrupt Level 22

Interrupt Level of INT [22] (Default: 000)

These bits specify the interrupt level of PCIERR0 interrupts.

000: Interrupt level 0 (Interrupt disabled)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

15:11

⎯

Reserved

⎯

10:8

IL7

Interrupt level 7

Interrupt Level of INT [7] (Default: 000)

These bits specify the interrupt level of external INT[5].

000: Interrupt level 0 (Interrupt disabled)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

7:3

⎯

Reserved

⎯

Figure 15.4.7 Interrupt Level Register 3 (1/2)

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