TMPR4937 datasheet(463/552 Pages) TOSHIBA

463 / 552 page

Chapter 15 Interrupt Controller

15-17

15.4.4 Interrupt Level Register 0 (IRLVL0)

0xF610

Reserved

IL17

Reserved

IL16

R/W

: Type

000

: Default

Reserved

IL1

Reserved

IL0

R/W

: Type

000

: Default

Bit

Mnemonic

Field Name

Explanation

Read/Write

31:27

⎯

Reserved

⎯

26:24

IL17

Interrupt Level 17

Interrupt Level of INT [17] (Default: 000)

These bits specify the interrupt level of [TMR [0]

000: Interrupt Level 0 (Interrupt disable)

001:Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

23:19

⎯

Reserved

⎯

18:16

IL16

Interrupt Level 16

Interrupt Level of INT [16] (Default: 000)

These bits specify the interrupt level of PCIC0 interrupts.

000: Interrupt level 0 (Interrupt disable)

001: Interrupt level 1

010: Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

15:11

⎯

Reserved

⎯

10:8

IL1

Interrupt Level 1

Interrupt Level of INT [1] (Default: 000)

These bits specify the interrupt level for TX49 Write Timeout Error

interrupts.

000: Interrupt level 0 (Interrupt disable)

001: Interrupt level 1

010:Interrupt level 2

011: Interrupt level 3

100: Interrupt level 4

101: Interrupt level 5

110: Interrupt level 6

111: Interrupt level 7

R/W

7:3

⎯

Reserved

⎯

Figure 15.4.4 Interrupt Level Register 0 (1/2)

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