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TMPR4937 Datasheet(PDF) 460 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 460 Page - Toshiba Semiconductor

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Chapter 15 Interrupt Controller
15-14
15.4.3 Interrupt Detection Mode Register 1 (IRDM1)
0xF608
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IC31
IC30
IC29
IC28
IC27
IC26
IC25
IC24
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Type
0
0
0
0
0
0
0
0
: Default
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IC15
IC14
IC13
IC12
IC11
IC10
IC9
IC8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
: Type
0
0
0
0
0
0
0
0
: Default
Bit
Mnemonic
Field Name
Explanation
Read/Write
31:30
IC31
Interrupt Source
Control 31
Interrupt Source Control 31 (Default: 00, R/W)
These bits specify the active state of SPI interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
29:28
IC30
Interrupt Source
Control 30
Interrupt Source Control 30 (Default: 00, R/W)
These bits specify the active state of DMA1[3] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
27:26
IC29
Interrupt Source
Control 29
Interrupt Source Control 29 (Default: 00, R/W)
These bits specify the active state of DMA1[2] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
25:24
IC28
Interrupt Source
Control 28
Interrupt Source Control 28 (Default: 00, R/W)
These bits specify the active state of DMA1[1] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
23:22
IC27
Interrupt Source
Control 27
Interrupt Source Control 27 (Default: 00, R/W)
These bits specify the active state of DMA1[0] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
21:20
IC26
Interrupt Source
Control 26
Interrupt Source Control 26 (Default: 00, R/W)
These bits specify the active state of PCIC1 interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
Figure 15.4.3 Interrupt Detection Mode Register 1 (1/3)



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