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TMPR4937 Datasheet(PDF) 458 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 458 Page - Toshiba Semiconductor |
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458 / 552 page ![]() Chapter 15 Interrupt Controller 15-12 15.4.2 Interrupt Detection Mode Register 0 (IRDM0) 0xF604 31 30 29 28 27 24 23 22 21 20 19 18 17 16 IC23 IC22 IC21 Reserved IC19 IC18 IC17 IC16 R/W R/W R/W R/W R/W R/W R/W : Type 0 0 0 0 0 0 0 : Default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0 R/W R/W R/W R/W R/W R/W R/W R/W : Type 0 0 0 0 0 0 0 0 : Default Bits Mnemonic Field Name Explanation Read/Write 31:30 IC23 Interrupt Source Control 23 Interrupt Source Control 23 (Default: 00) These bits specify the active state of PCIPMC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable R/W 29:28 IC22 Interrupt Source Control 22 Interrupt Source Control 22 (Default: 00) These bits specify the active state of PCIERR0 interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable R/W 27:26 IC21 Interrupt Source Control 21 Interrupt Source Control 21 (Default: 00) These bits specify the active state of NDFMC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable R/W 25:24 ⎯ ⎯ Reserved ⎯ 23:22 IC19 Interrupt Source Control 19 Interrupt Source Control 19 (Default: 00) These bits specify the active state of TMR[2] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable R/W 21:20 IC18 Interrupt Source Control 18 Interrupt Source Control 18 (Default: 00) These bits specify the active state of TMR[1] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable R/W 19:18 IC17 Interrupt Source Control 17 Interrupt Source Control 17 (Default: 00) These bits specify the active state of TMR[0] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable R/W Figure 15.4.2 Interrupt Detection Mode Register 0 (1/2) |
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