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TMPR4937 Datasheet(PDF) 461 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 461 Page - Toshiba Semiconductor

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Chapter 15 Interrupt Controller
15-15
Bit
Mnemonic
Field Name
Explanation
Read/Write
19:18
IC25
Interrupt Source
Control 25
Interrupt Source Control 25 (Default: 00, R/W)
These bits specify the active state of ACLCPME interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
17:16
IC24
Interrupt Source
Control 24
Interrupt Source Control 24 (Default: 00, R/W)
These bits specify the active state of ACLC interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
15:14
IC15
Interrupt Source
Control 15
Interrupt Source Control 15 (Default: 00)
These bits specify the active state of PDMAC interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
13:12
IC14
Interrupt Source
Control 14
Interrupt Source Control 14 (Default: 00)
These bits specify the active state of IRC interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
11:10
IC13
Interrupt Source
Control 13
Interrupt Source Control 13 (Default: 00)
These bits specify the active state of DMA0 [3] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
9:8
IC12
Interrupt Source
Control 12
Interrupt Source Control 12 (Default: 00)
These bits specify the active state of DMA0 [2] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
7:6
IC11
Interrupt Source
Control 11
Interrupt Source Control 11 (Default: 00)
These bits specify the active state of DMA0 [1] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
5:4
IC10
Interrupt Source
Control 10
Interrupt Source Control 10 (Default: 00)
These bits specify the active state of DMA0 [0] interrupts.
00: Low level active
01: Disable
10: Disable
11: Disable
R/W
Figure 15.4.3 Interrupt Detection Mode Register 1 (2/3)



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