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TMPR4937 Datasheet(PDF) 519 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 519 Page - Toshiba Semiconductor

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Chapter 21 Electrical Characteristics
21-13
21.5.10 SIO Interface AC characteristics
(Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V)
Item
Symbol
Conditions
Min.
Max.
Unit
Boot configuration
ADDR[2]=H
4
× tMCP × 1.1
⎯
ns
SCLK Cycle time
fCYC_SCLK
Boot configuration
ADDR[2]=L
tMCP × 1.1
⎯
ns
Boot configuration
ADDR[2]=H
⎯
1/2
× fMCK × 0.45
MHz
SCLK Frequency
fSCLK
Boot configuration
ADDR[2]=L
⎯
2
× fMCK × 0.45
MHz
Boot configuration
ADDR[2]=H
2
× tMCP × 1.1
⎯
ns
SCLK High Time
tHIGH_SCLK
Boot configuration
ADDR[2]=L
1/2
× tMCP × 1.1
⎯
ns
Boot configuration
ADDR[2]=H
2
× tMCP × 1.1
⎯
ns
SCLK Low Time
tLOW_SCLK
Boot configuration
ADDR[2]=L
1/2
× tMCP × 1.1
⎯
ns
Figure 21.5.11 Timing Diagram: SIO Interface
21.5.11 Timer Interface AC characteristics
(Tc = 0 – 70
°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V)
Item
Symbol
Conditions
Min.
Max.
Unit
Boot configuration
ADDR[2]=H
4
× tMCP × 1.1
⎯
ns
TCLK Cycle Time
fCYC_TCLK
Boot configuration
ADDR[2]=L
tMCP × 1.1
⎯
ns
Boot configuration
ADDR[2]=H
⎯
1/2
× fMCK × 0.45
MHz
TCLK Frequency
fTCLK
Boot configuration
ADDR[2]=L
⎯
2
× fMCK × 0.45
MHz
Boot configuration
ADDR[2]=H
2
× tMCP × 1.1
⎯
ns
TCLK High Time
tHIGH_TCLK
Boot configuration
ADDR[2]=L
1/2
× tMCP × 1.1
⎯
ns
Boot Configuration
ADDR[2]=H
2
× tMCP × 1.1
⎯
ns
TCLK Low Time
tLOW_TCLK
Boot configuration
ADDR[2]=L
1/2
× tMCP × 1.1
⎯
ns
Figure 21.5.12 Timing Diagram: Timer Interface
tHIGH_SCLK
SCLK
tLOW_SCLK
tCYC_SCLK/fSCLK
tHIGH_TCLK
TCLK
tLOW_TCLK
tCYC_TCLK/fTCLK



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