TMPR4937 datasheet(545/552 Pages) TOSHIBA

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TMPR4937 Revision History

Page

Rev 1.1 Manual

Changes and Additions to Rev 1.1

References

64-bit TX System RISC TX49/H3 Core Architecture User’s

Manual

64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core

Architecture

1-1

Modified line 5 of the body text in Section 1.1, Overview

For details of the TX49/H3 core such as instruction sets, see

“64-bit TX System RISC TX49/H3 Core Architecture”.

For details of the TX49/H3 core such as instruction sets,

see “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4

Core Architecture”.

3-7

Table 3.1.9 AC-link Interface Signals

Added the following text to the description of the SDIN[1]

signal

When this pin is used as SDIN[1], pull down by the resister

on the board. (Regarding the value of register, please ask

the Engineering Department in Toshiba).

3-7

Table 3.1.9 AC-link Interface Signals

Added the following text to the description of the SDIN[0]

signal

When this pin is used as SDIN[0], pull down by the resister

on the board. (Regarding the value of register, please ask

the Engineering Department in Toshiba).

3-7

Table 3.1.9 AC-link Interface Signals

Added the following text to the description of the BITCLK

signal

When this pin is used as BITCLK, pull down by the resister

on the board. (Regarding the value of register, please ask

the Engineering Department in Toshiba).

3-8

Table 3.1.11 Extended EJTAG Interface Signals

Changed the description of the TRST* signal

When an EJTAG probe is not connected, this pin must be

fixed to low. When connecting an EJTAG probe, prevent

floating, for example, by connecting a pull-up resistor.

TRST* pin must be pulled down (ex.10 k

Ω).

3-11

Table 3.2.2 Boot Configuration Specified with the

ADDR[19:0] Signals (1/2)

Modified the description of the ADDR[17:15].

Reserved

Used for testing. This signal will not be set to 0 upon

booting.

4-1

Modified line 2 of the introduction in Chapter 4, Address

Mapping

Please refer to "64 bit TX System RISC TX49/H3 Core

Architecture" about the details of mapping to a physical

address from the virtual address of TX49/H3 core.

Please refer to "64-bit TX System RISC TX49/H2, TX49/H3,

TX49/H4 Core Architecture" about the details of mapping to

a physical address from the virtual address of TX49/H3

core.

5-2

Table 5.2.1 Configuration Register Mapping

Deleted the description of the Jump Address Register

Deleted

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