TMPR4937 datasheet(549/552 Pages) TOSHIBA

549 / 552 page

TMPR4937 Revision History

Page

Rev 1.1 Manual

Changes and Additions to Rev 1.1

8-13

Table 8.3.3 Channel Register Setting Restrictions During

Dual Address Transfer

8/0/-8

8-13

Table 8.3.3 Channel Register Setting Restrictions During

Dual Address Transfer

Added the following note.

:When DMSAIRn is set to 0, read access from source

device is performed only one time per transmission

specified by DMCCRn.XFSZ. For this reason, transfer

can not be performed burst transfer to the I/O device

which performs FIFO operation.

9-23

Figure 9.4.4 ECC Control Register (1/2)

0x10

MDLNO

0x10

9-23

Figure 9.4.4 ECC Control Register (1/2)

0x10

VERNO

0x10

9-23

Figure 9.4.4 ECC Control Register (1/2)

Modified the description of the DEEC (Diagnostic ECC)

field.

The value set by this field is output from CB[7:0] as the

check code when the ECCDM bit is set to “Enable.”

The value set by this field is output from CB[7:0] as the

check code when the DM bit is set to “Enable.”

9-25

Figure 9.4.5 ECC Status Register

FRRS

—

ERRS

—

9-42

Figure 9.6.2 168-pin DIMM Connection Example

ADDR[18]

ADDR[16:5]

ADDR[17]

128MB un

A[11:0]

BA0

BA1

DQMB[7:0]

ADDR[19]

ADDR[16:5]

ADDR[18]

128MB un

A[11:0]

BA0

BA1

DQMB[7:0]

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