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TMPR4937 Datasheet(PDF) 551 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 551 Page - Toshiba Semiconductor

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TMPR4937 Revision History
7
Page
Rev 1.1 Manual
Changes and Additions to Rev 1.1
20-7
Modified line 8 of Section 20.3, Initializing the Extended
EJTAG Interface
The above methods must be performed while the
MASTERCLK signal is being input. Also, externally fix
the TRST* signal to GND when not using an emulation
probe. The G-Bus Time Out Detection function is disabled
when the TRST* signal is deasserted. (Refer to Section
5.1.1.)
The above methods must be performed while the
MASTERCLK signal is being input.
The G-Bus Time Out Detection function is disabled when
the TRST* signal is deasserted. (Refer to Section 5.1.1.)
21-5
Figure 21.5.1 Timing Diagram: MASTERCLK
tMCP
MASTERCL
0.8 VCC
0.2 VCC
tMCP
MASTERCLK
0.8 VCC
0.2 VCC
21-5
Figure 21.5.2 Timing Diagram: Power On Reset
tMCP_PLL
MASTERCLK Oscillation Stabilit
VddIN, VddIO
PLL_Vdd1_A,
PLL_Vdd2_A
MASTERCLK
CGRESET*
RESET*
Changed a signal name in the figure and added a note.
tMCP_PLL
MASTERCLK Oscillation Stabilit
VCCInt, VCCIO
*1)
PLL_Vdd1_A,
PLL_Vdd2_A
MASTERCLK
CGRESET*
RESET*
*1)
VCCInt and VCCIO must start up simultaneously, or
VCCInt must be first.
The difference of the stand up time of a power supply
within in 100 m seconds.
22-2
Figure 22.1.1 Pinout Diagram (1/2)
7 DMAACK
[2]
DMAACK
[3]
CE[1]*
CE[0]*
VddIO
6 CE[4]*
CE[3]*
CE[2]*
VSS
SD[1]
TOP
5 CE[5]*
VddIO
ACE*
BYPASSP
LL*
VSS
VddIN
7 DMAACK
[2]
DMAACK
[3]
CE[1]*
CE[0]*
VddIO
6 CE[4]*
CE[3]*
CE[2]*
VSS
SDIN[1]
TOP
5 CE[5]*
VddIO
ACE*
BYPASSP
LL*
VSS
VddIN
22-4
Table 22.1.1 Pin Cross Reference by Pin Number (1/2)
Modified the pin name of the E6 pin.
SD[1]
SDIN[1]
22-7
Table 22.1.2 Pin Cross Reference by Pin Name (2/2)
Modified the pin name of the E6 pin.
SD[1]
SDIN[1]



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