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TMPR4938 Datasheet(PDF) 413 Page - Toshiba Semiconductor

Part # TMPR4938
Description  64-Bit TX System RISC TX49 Family
PDF  716 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4938 Datasheet(HTML) 413 Page - Toshiba Semiconductor

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Chapter 12 Timer/Counter
12-11
12.4.2 Timer Interrupt Status Register n (TMTISRn)
TMTISR0 0xF004
TMTISR1 0xF104
TMTISR2 0xF204
31
16
Reserved
: Type
: Initial value
15
4
3
2
1
0
Reserved
TWIS TPIBS TPIAS
TIIS
RW0C RW0C RW0C RW0C : Type
0
0
0
0
: Initial value
Bit
Mnemonic
Field Name
Description
Read/Write
31:4
Reserved
⎯
3
TWIS
Watchdog Timer
Status
Watchdog Timer TMCPRA Match Status (Default: 0)
(This bit is Reserved in the case of the TMTISR0 Register and the TMTISR1
Register.)
When in the Watchdog Timer mode, this bit is set when the counter value
matches Compare Register 2 (TMCPRA2).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Negate interrupt
1: Invalid
R/W0C
2
TPIBS
Pulse Generator
TMCPRB Status
Pulse Generator TMCPRB Match Status (Default: 0)
(This bit is Reserved in the case of the TMTISR2 Register.)
When in the Pulse Generator mode, this bit is set when the counter value
matches Compare Register Bn (TMCPRBn).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
R/W0C
1
TPIAS
Pulse Generator
TMCPRA Status
Pulse Generator TMCPRA Match Status (Default: 0)
(This bit is Reserved in the case of the TMTISR2 Register.)
When in the Pulse Generator mode, this bit is set when the counter value
matches Compare Register A n (TMCPRAn).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
R/W0C
0
TIIS
Interval Timer
TMCPRA Status
Interval Timer TMCPRA Match Status (Default: 0)
When in the Interval Timer mode, this bit is set when the counter value
matches Compare Register A n (TMCPRAn).
This bit is cleared by writing a “0” to it.
During Read
0: Did not match the Compare Register
1: Matched the Compare Register
During Write
0: Clear
1: Invalid
R/W0C
Figure 12.4.2 Timer Interrupt Status Register



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