TMPR4938 datasheet(244/716 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-10

9.3.4

Initialization of Memory Data, ECC/Parity

The SDRAMC has functions for simultaneously performing Memory Writes to multiple memory

channels. These functions are effective when quickly initializing data memory or ECC/parity memory.

Channels for which both the Channel Enable bit (SDCCRn.CE) and the Master Enable bit

(SDCCRn.ME) of the SDRAM Channel Control Register are set become the Master channel. Also,

channels for which both the Channel Enable bit (SDCCRn.CE) and the Slave Enable bit (SDCCRn.SE)

are set become the Slave channel. See Table 9.3.4 Master/Slave Channel Settings for information

regarding the Master/Slave channel settings.

The slave channel is simultaneously written to when the Master channel is written to. Settings of the

Master channel are used when in the ECC/Parity mode. Please set to the same value the SDRAM

settings of all channels that are simultaneously written to.

Using the DMA Controller and performing 32 double word Burst access is the most efficient way to

access the Master channel. The DMAC has registers for setting memory initialization data. When the

DMAC is launched by an internal request when in the Single address IO

→Memory Transfer mode, the

data set in this register are written to memory. See Chapter 8 "DMA Controller" for more information.

Table 9.3.4 Master/Slave Channel Settings

SDCCRn.CE

(Channel Enable)

SDCCRn.ME

(Master Enable)

SDCCRn.SE

(Slave Enable)

Description

Channel is disabled.

Normal operation is performed.

When a Write operation is executed by a channel

where SDCCRn.ME

=1, the Write operation is also

executed by this channel.

Normal operation is performed when this channel is

Active.

When a Write operation is executed by this channel,

the Write operation is simultaneously executed by all

channels where SDCCRn.SE

=1.

When a Write operation is executed by this channel,

the Write operation is simultaneously executed by all

channels where SDCCRn.SE

=1.

A Write operation is also simultaneously executed by

this channel when the Write operation is executed by

another channel where SDCCRn.ME

=1.

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