TMPR4938 datasheet(247/716 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-13

9.3.10 ECC

9.3.10.1 ECC/Parity Mode

Table 9.3.5 shows the supported ECC/Parity functions. The ECC/Parity mode can be set

separately for each channel using the ECC/Parity Mode field (SDCCRn.ECC) of the SDRAM

Channel Control Register. The ECC enable bit (ECCCR.ECCE) of the ECC Control Register must

be set in order to use the ECC function. No error detection, logging, or notification will be

performed if this bit is not set.

Table 9.3.5 ECC/Parity Mode

ECC Field

Mode Name

Description

0x0

NOP Mode

Disables the ECC/Parity function.

0x1

EC Mode

EC (Error Check) enable

Read: Performs only error checking. Correction is not performed.

Write: Generates check code.

0x2

ECC Mode

ECC (Error Check and Correct) enable

Read: Performs error checking and correction.

Write: Generates check code.

0x3

ECC + Scrub Mode

ECC + scrub enable

Read: Performs error checking and correction. Corrected data is written back to

memory if an error occurs.

Write: Generates check code.

0x4

Even Parity Mode

Even parity enable

Read: Performs error checking.

Write: Generates even parity.

0x5

Odd Parity Mode

Odd parity enable

Read: Performs error checking.

Write: Generates odd parity.

0x6

—

Reserved

0x7

—

Reserved

•

The ECC/Parity Mode changes dynamically according to each channel setting.

•

Error checking is performed when writing data smaller than 64 bits when Memory Read

access is being performed while in the EC Mode, ECC Mode, or ECC + scrub mode.

•

Data correction is performed if the read data cause a single-bit error when in the ECC Mode

or the ECC + scrub mode. Data is read unchanged when in any other mode regardless of

whether or not an error occurs.

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