ADF4378 datasheet(32/84 Pages) AD

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Data Sheet

ADF4378

THEORY OF OPERATION

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Rev. A | 32 of 84

Table 24. Double Buffer Enable Bits and Bit Fields

Double Buffer Enable Bits

Double Buffered Bit Fields

Not applicable, always enabled

N_INT bits, Bits[11:0], R_DIV,

EN_RDBLR, CP_I

CLKODIV_DB

CLKOUT_DIV

DCLK_DIV_DB

DCLK_DIV1, DCLK_DIV2

O_VCO_DB

M_VCO_CORE, M_VCO_BAND,

M_VCO_BIAS

DEL_CTRL_DB

INV_CLKOUT, BLEED_I bits, Bits[9:0],

BLEED_POL, N_DEL, R_DEL

Serial Port

The SPI-compatible serial port provides control and monitoring

functionality. The CMOS_OV bit determines if the logic high level

for the SDO and SDIO SPI output pins is 3.3 V or 1.8 V. CMOS_OV

also sets the output level for MUXOUT and LKDET.

The serial port can be programmed to support several different

configurations in REG0000 and REG0001.

The SDO_ACTIVE bit determines if the serial port is configured as

a 3-wire or 4-wire serial interface (see the timing diagrams Figure 2,

Figure 3, and Figure 4).

As shown in Figure 82 and Figure 83, the instruction cycle is

composed of 16 bits. The fifteen LSB bits determine the register

address, and the MSB determines if data is written to or read from

the serial interface during the data transfer cycle. The LSB_FIRST

bit determines the data orientation of the instruction cycle and data

transfer cycle of the serial interface.

Figure 82. Serial Interface, MSB First (LSB_FIRST = 0)

Figure 83. Serial Interface, LSB First (LSB_FIRST = 1)

The SPI register map can be programmed with single instructions,

as shown in Figure 82 and Figure 83, or in streaming mode,

as shown in Figure 84. Streaming mode allows for efficient data

transfer read or write cycles to multiple registers. Streaming mode

allows the user to program a bit stream composed of one register

address in the instruction header and data for that register address,

which is then followed by data in subsequent register addresses.

The ADDRESS_ASCENSION bit determines if the subsequent reg-

ister addresses are incremented or decremented. It is recommend-

ed to decrement the register addresses in streaming mode (AD-

DRESS_ASCENSION = 0). The reason for this recommendation is

because REG0010 triggers the VCO calibration and loading of all

double buffers and, therefore, must be the last SPI register written

to. The SINGLE_INSTRUCTION bit disables streaming mode when

it is set to 1. When SINGLE_INSTRUCTION is set to 0, streaming

mode is enabled.

Block Power-Down Control

The power-down control bits of the ADF4378 reside in REG0019

and REG001A. The PD_ALL, PD_RDET, PD_CLKOUT, and

PD_SYSOUT bits may be programmed independently.

The PD_CLK, PD_CALDAC, PD_RDIV, PD_NDIV, PD_VCO,

PD_LD, and PD_PFDCP bits must be set to the same state at

all times. The only time this group is allowed to be set to 1 is when

a full power-down ambient temperature measurement is performed

(see Table 23). In all other cases, this bit grouping must be set to 0.

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