ADF4378 datasheet(1/84 Pages) AD

Part #	ADF4378

Description	Microwave Wideband Synthesizer with Integrated VCO and Deterministic General- Purpose Pulse Retimer

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Data Sheet

ADF4378

Microwave Wideband Synthesizer with Integrated VCO and Deterministic General-

Purpose Pulse Retimer

Rev. A

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FEATURES

►

Output frequency range: 800 MHz to 12.8 GHz

►

Jitter = 18 fsRMS (integration bandwidth: 100 Hz to 100 MHz)

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Jitter = 27 fsRMS (ADC SNR method)

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Wideband noise floor: −160 dBc/Hz at 12 GHz

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Retimed LVDS SYSREF output

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General-purpose pulse retimer for SYSREF, SYNC, and MCS

applications

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PLL specifications

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−239 dBc/Hz: normalized in-band phase noise floor

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−147 dBc/Hz: normalized in-band 1/f phase noise floor

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Phase detector frequency up to 500 MHz

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Reference input frequency up to 1000 MHz

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Typical spurious fPFD: −95 dBc PFD at fOUT = 12 GHz

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Reference input to output delay specifications

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Device-to-device standard deviation: 3 ps

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Temperature coefficient: 0.03 ps/°C

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Adjustment step size: < ±0.1 ps

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Multichip output phase alignment

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3.3 V and 5 V power supplies

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Available in 48-lead, 7 mm × 7 mm LGA package

APPLICATIONS

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High performance data converter and MxFE clocking

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Wireless infrastructure (MC-GSM, 5G)

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Test and measurement

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FPGA with integrated data converters

GENERAL DESCRIPTION

The ADF4378 is a high performance, ultra-low jitter, integer-N

phased locked loop (PLL) with an integrated voltage controlled

oscillator (VCO) and system reference (SYSREF) retimer ideally

suited for data converter and mixed signal front end (MxFE) clock

applications. The high performance PLL has a −239 dBc/Hz: nor-

malized in-band phase noise floor, ultra-low 1/f noise, and a high

phase/frequency detector (PFD) frequency that can achieve ultra-

low in-band noise and integrated jitter. The fundamental VCO and

output divider of the ADF4378 generate frequencies from 800 MHz

to 12.8 GHz. The ADF4378 integrates all necessary power-supply

bypass capacitors, which saves board space on compact boards.

For multiple data converter and MxFE clock applications, the

ADF4378 simplifies clock alignment and calibration routines re-

quired with other clock solutions by implementing the automatic

reference to output synchronization feature, the matched reference

to output delays across process, voltage, and temperature feature,

and the less than ±0.1 ps, jitter free reference to output delay

adjustment capability feature.

The general-purpose pulse retimer feature allows for predicta-

ble and precise multichip clock and pulse alignment for SYS-

REF, SYNC, and multichip synchronization (MCS) architectures.

JESD204B and JESD204C Subclass 1 solutions are supported by

pairing the ADF4378 with an integrated circuit (IC) that distributes

pairs of reference and SYSREF signals. The pulse retimer feature

simplifies the system design by allowing the widely distributed

SYSREF to only meet the slower reference frequency timing vs.

the much more stringent output clock timing. Serial-peripheral

interface (SPI) selectable current-mode logic (CML)/low-voltage

positive/pseudo emitter-coupled logic (LVPECL) or low-voltage dif-

ferential signaling (LVDS) SYSREF input and LVDS SYSREF out-

put allow CML to LVDS signal conversion, which simplifies clock

and SYSREF alignment for various converters. The pulse retimer

feature also can be used with transceiver MCS signals and SYNC

signals for other ICs.

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