ADF4378 datasheet(26/84 Pages) AD

26 / 84 page

Data Sheet

ADF4378

THEORY OF OPERATION

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Rev. A | 26 of 84

Table 12. CP Programming (Continued)

CP_I, Bits[3:0]

ICP

4.77 mA

5.57 mA

6.33 mA

7.91 mA

9.51 mA

11.1 mA

Charge-Pump Test Mode

When the EN_CPTEST bit is set to 1, the CP_UP bit and

CP_DOWN bit can be programmed to force a constant ICP source

or sink current, respectively, on the CP pin. These bits are com-

monly used as an aid to debug PLL related issues during the

hardware and software development phase of a project. For normal

operation, set EN_CPTEST, CP_UP, and CP_DOWN to 0. For more

information, see Figure 69 and Table 13.

Table 13. Charge-Pump Debug Functions

EN_CPTEST

CP_UP

CP_DOWN

CP Pin State Debug Test

High-Z

VCO open loop

~VV5_CP

Charge-pump

output voltage

verification

~GND

Normal oper-

ation

Not applicable

Charge-Pump Bleed Current

A small programmable constant charge-pump current, known as

bleed current, can be used to either increase or decrease the

propagation delay from the reference input pins to the clock output

pins.

To enable the bleed current, set the EN_BLEED bit to 1. When

the BLEED_POL bit is set to 1, a small constant source current is

forced onto the CP pin. When the BLEED_POL is set to 0, a small

constant sink current is forced onto the CP pin (see Figure 69).

The bleed-current LSB step size is 536 nA. The bleed-current delay

step size (tIDEL-STEP) is a function of the bleed-current step size

(ICP) and fPFD, as shown in Equation 9. Figure 70 provides a quick

reference of tIDEL-STEP vs. several common ICP and fPFD values.

tIDEL−STEP= 536 nA

ICP×fPFD

(9)

Figure 70. Bleed-Current Delay Step Size

Bleed-current delay (tIDEL) is determined by tIDEL-STEP, the

BLEED_POL bit, and BLEED_I bit fields, Bits[9:0] (see Equation

10 and Equation 11).

If BLEED_POL = 0, the propagation delay from the REFP and

REFN input pins to the CLKP and CLKN output pins increases (see

Figure 21).

tIDEL=tIDEL−STEP×BLD_I

(10)

where BLD_I represents the decimal value of the BLEED_I bit field,

Bits[9:0].

If BLEED_POL = 1, the propagation delay from the REFP and

REFN input pins to the CLKP and CLKN output pins decreases

(see Figure 24).

tIDEL=−tIDEL−STEP×BLD_I

(11)

The maximum tIDEL for proper lock detector functionality is based

on the LDWIN_PW setting, as shown in Table 16.

INV_CLKOUT, BLEED_I, and BLEED_POL can be used in conjunc-

tion to align the multichip output-to-output skew to as small as

±0.05 ps (see Equation 9). The largest BLEED_I settings may

increase LNORM by 1 dB and L1/f by 4 dB, as shown in Figure 42.

INV_CLKOUT does not degrade performance and must be used to

adjust for multichip output-to-output skews greater than a quarter of

the 1/fOUT period, in lieu of a large BLEED_I value. As a result, the

maximum tIDEL adjustment never needs to be more than a quarter

of the 1/fOUT period. For the relationship between R_DEL, N_DEL,

INV_CLKOUT, BLEED_I bit fields, Bits[9:0], and BLEED_POL, see

the Applications Information section.

Lock Detector

The lock detector uses internal signals from the PFD to measure

phase coincidence between the output signal of the reference

divider and doubler (RCLK) in Figure 66 and the output signal of

the feedback divider (NCLK) in Figure 76. It is enabled by setting

both the EN_LOL bit and the EN_LDWIN bit to 1 and presents the

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