ADF4378 datasheet(29/84 Pages) AD

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Data Sheet

ADF4378

THEORY OF OPERATION

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Rev. A | 29 of 84

7. After the VCO calibration is complete, disable calibration clocks

to limit unwanted spurious content by setting EN_DRCLK =

EN_DNCLK = EN_ADC_CLK = 0.

8. This is an optional step. Read back the VCO_CORE,

VCO_BAND, and VCO_BIAS bits, and then record the read-

back values. These values can be used to bypass calibration

and manually program the M_VCO_CORE, M_VCO_BAND,

and M_VCO_BIAS bits for a given device and frequency, as

described in the Fast Power-Up and Initialization, Manually

Programmed VCO Calibration Settings (Optional) section.

Table 17. CAL_CT_SEL, DCLK_DIV2, and DCLK_MODE Setup

fPFD (MHz)

CAL_CT_

SEL

DCLK_DIV2

DCLK_MOD

fDIV_RCLK

(MHz)

≤160

fPFD/2

>160 and ≤250

fPFD/2

>250 and ≤320

fPFD/4

>320 and ≤500

fPFD/4

Clock Output Divider

A 2-bit divider, CLKOUT_DIV, in Figure 73 is used to reduce

the frequency seen at the output buffer and feedback divider.

The clock output divide value (O) may be set to 1, 2, 4, or 8.

Use the CLKOUT_DIV bit to directly program the divide ratio.

CLKOUT_DIV is located inside the PLL loop. Therefore, any

change to CLKOUT_DIV requires a change to the N_INT bit fields,

Bits[11:0] to maintain the same fPFD and results in the PLL losing

lock for a few loop time constants. For more information, see Table

18. For the relationship between the fREF, fPFD, fVCO, and fOUT

frequencies, see the Output Frequency section.

Table 18. CLKOUT_DIV Programming

CLKOUT_DIV

Clock Output Divide Value

(O)

Output Frequency Range

(GHz)

6.4 ≥ fOUT ≤ 12.8

3.2 ≥ fOUT ≤ 6.4

1.6 ≥ fOUT ≤ 3.2

0.8 ≥ fOUT ≤ 1.6

Output Invert (INV_CLKOUT)

The output invert (INV_CLKOUT) is used to shift the output signal

180° with respect to the rising edge of the reference input signal,

when fOUT is an integer multiple of fREF. For more information, see

Table 19. INV_CLKOUT is located inside the PLL loop, and any

change to INV_CLKOUT results in the PLL losing lock for few a

loop time constants. Use the INV_CLKOUT bit to directly program

the output phase.

Table 19. INV_CLKOUT Programming

fOUT/fREF =

INV_CLKOUT

Each Reference Rising Edge Aligned

Integer

CLKP rising edge

Integer

CLKP falling edge

Table 19. INV_CLKOUT Programming (Continued)

fOUT/fREF =

INV_CLKOUT

Each Reference Rising Edge Aligned

Noninteger

Varies

INV_CLKOUT, N_DEL, R_DEL, BLEED_I, and BLEED_POL can be

used in conjunction to align the multichip output-to-output skew to

sub ps levels. INV_CLKOUT does not degrade performance and

must be used to adjust for multichip output-output skews greater

than a quarter of the 1/fOUT period, in lieu of a large N_DEL,

R_DEL, or BLEED_I value. For the relationship between R_DEL,

N_DEL, INV_CLKOUT, BLEED_I, and BLEED_POL, see the Align-

ing Multiple ADF4378 Output Phases section.

Feedback Divider (N)

A 12-bit divider, the N_INT bit fields, Bits[11:0], in Figure 76, is

used to reduce the frequency seen at the output of the clock output

divider. The feedback divider closes the feedback loop from the

VCO and clock output divider to the PFD.

Figure 76. Feedback Divider

The feedback divider divide ratio (N) may be programmed to any

integer from 2 to 4095. Use the N_INT bit fields, Bits[11:0] to direct-

ly program the N divide ratio (see Table 20). For the relationship

between N, O, and the fREF, fPFD, fVCO, and fOUT frequencies, see

the Output Frequency section. The state of the DCLK_MODE bit is

determined by Table 17.

Table 20. N_INT Programming

N_INT Bit Fields, Bits[11:0]

Not applicable

…

4095

Feedback Delay

A 7-bit delay, N_DEL, is used to decrease the propagation delay

from the REFP and REFN input pins to the CLKP and CLKN output

pins. Use the N_DEL bits to directly program the feedback delay

(tNDEL), which typically ranges from 0 ps to 110 ps in 0.85 ps steps

(see Figure 77).

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