ADF4378 datasheet(12/84 Pages) AD

12 / 84 page

Data Sheet

ADF4378

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

analog.com

Rev. A | 12 of 84

Table 6. Pin Function Descriptions (Continued)

Pin Number

Mnemonic

Description

CSB

Serial-Port Chip Select. 1.8 V and 3.3 V compatible CMOS input. This CMOS input initiates a serial-port communication burst when driven

low, which ends the burst when driven back high.

SDIO

Serial Data Input/Output. 1.8 V and 3.3 V programmable CMOS input/output. When configured as an input, the serial port uses this CMOS

input for data. In 3-wire readback mode (default mode), this pin outputs data from the serial port during a read communication burst.

SCLK

Serial-Port Clock. 1.8 V and 3.3 V compatible. This CMOS input clocks serial-port input data on its rising edge.

SDO

Optional Serial Data Output. 1.8 V and 3.3 V programmable CMOS output. In 3-wire mode (default mode), this three state CMOS pin

remains in a high impedance state. In 4-wire readback mode, this pin presents data from the serial port during a read communication

burst. When the CSB is deasserted, SDO returns to a high impedance. Optionally, attach a resistor of > 200 kΩ to prevent a floating

output.

V3_LDO

3.15 V to 3.45 V Positive Power Supply Pin for the Internal LDO Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 1.

MUXOUT

Internal Device Mux Output. This output pin can be connected to multiple internal nodes for factory test and debug purposes.

38, 39

SR_INP,

SR_INN

SYSREF Input. This input reclocks a reference aligned SYSREF signal to a known clock period on the SR_OUTP and SR_OUTN pins.

DC-coupled common ranges that support CML, LVPECL, or LVDS can be selected through the serial port.

V3_SRIN

3.15 V to 3.45 V Positive Power Supply. Short this pin to the other pins in 3.3 V Power Supply Group 1.

42, 43

REFP, REFN

Reference Input Signal. This differential input is buffered with a delay matched amplifier (DMA) for well controlled reference to output

propagation delays (default mode, REF_SEL = 0). For low slew-rate reference input signals, an alternate low noise amplifier (LNA) can

be selected through the serial port (REF_SEL = 1). Reference inputs are self-biased and must be AC-coupled with 1 μF capacitors.

Reference inputs accept differential or single-ended inputs.

V3_REF

3.15 V to 3.45 V Positive Power Supply Pin for the PLL Reference Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 1.

V3_PFD

3.15 V to 3.45 V Positive Power Supply Pin for PFD Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 1.

V5_CP

4.75 V to 5.25 V Positive Power Supply Pin for Charge Pump Circuitry. This pin must be isolated from the V5_VCO supply plane.

Charge Pump Output. This bidirectional current output is normally connected to the external loop filter.

Exposed Pad

Exposed Pad. Negative power supply (ground). The LGA has exposed paddle that must be connected to the ground pad. The PCB land

pattern must have multiple thermal vias to the ground plane for both low ground inductance and low thermal resistance.

ADF4378 Datasheet(PDF) 12 Page - Analog Devices

ADF4378 Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL