ADF4378 datasheet(23/84 Pages) AD

23 / 84 page

Data Sheet

ADF4378

THEORY OF OPERATION

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Rev. A | 23 of 84

INTRODUCTION

A PLL is a complex feedback system that may conceptually be

considered a frequency multiplier. The system multiplies the refer-

ence input frequency (fREF) and produces a higher frequency on

the clock output pins (fOUT). The PFD, charge pump, output divider,

feedback divider, VCO, and external loop filter forms a feedback

loop to accurately control the output frequency (see Figure 1). The

reference divider or reference doubler is used to set the frequency

resolution.

The ADF4378 has an additional input and output clock pair, which

is used to provide the retimed SYSREF clock to JESD204B/C devi-

ces. The SYSREF clock generated by an external clocking product

is retimed with the reference clock, feedback clock, and output

clock. This provides a well-controlled device clock and SYSREF

clock pair in which any effect coming from temperature or any

system level mismatched is compensated.

OUTPUT FREQUENCY

When EN_RDBLR = 0

When the loop is locked, the frequency (fVCO ) (in Hz) produced at

the output of the VCO is determined by the reference frequency

(fREF) and the O, R, and N values given by Equation 1. For more

information, see Table 11 and Table 18.

fVCO=fREF

×N×OR

(1)

In the following equation, the PFD frequency (fPFD) produced is

given by Equation 2.

fPFD

=fREFR

(2)

The fVCO may be alternatively expressed as:

fVCO=fPFD×N×O

(3)

The output frequency (fOUT) produced at the output of the output

divider is given by Equation 4.

fOUT=fVCOO

(4)

The output frequency resolution (fSTEP) produced by a unit change

in N is given by Equation 5.

fSTEP

=fPFD

(5)

When EN_RDBLR = 1

When the loop is locked, the frequency (fVCO ) (in Hz) produced at

the output of the VCO is determined by the reference frequency

(fREF) and the O, D, and N values given by Equation 6.

fVCO=fREF×D×N×O

(6)

When EN_RDBLR = 1, the PFD frequency (fPFD) produced is given

by Equation 7.

fPFD=fREF×D

(7)

Equation 3, Equation 4, and Equation 5 for fVCO, fOUT, and fSTEP

remain the same when EN_RDBLR = 1.

CIRCUIT DESCRIPTION

Reference Input Buffer

The reference frequency of the PLL is applied differentially on the

REFP and REFN pin. These high impedance inputs are self-biased

and must be AC-coupled with 1 µF capacitors (for a simplified

schematic, see Figure 65). Alternatively, the differential inputs may

be configured as a single ended input by applying the reference

frequency at REFP and bypassing REFN to GND with a 1 µF

capacitor (see Figure 85).

Figure 65. Reference Input Stage

A high quality signal must be applied to the REFP and REFN inputs

because they provide the frequency reference to the entire PLL.

To achieve the in-band phase noise performance of the PLL, apply

a continuous waveform signal or a square wave with a slew rate

of at least 1000 V/µs. For more information on reference input

signal requirements and interfacing, see the Reference Source

Considerations section.

When the REF_SEL bit is set to 0, the DMA buffer is selected. The

DMA is optimized for high slew rate signals, such as square waves

or higher frequency and higher amplitude sine waves. The DMA

has a controlled propagation delay from the reference input to clock

output, which eases time zero and over temperature multichip clock

alignment.

When the REF_SEL bit is set to 1, the LNA is selected. The LNA

is optimized for low slew rate signals, such as lower frequency or

lower amplitude sine waves.

The REF_SEL bit must be set correctly to optimize the in-band

phase noise performance and propagation delay. For recommend-

ed settings, see Table 7, Figure 43, and Equation 8.

Table 7. REF_SEL Programming

REF_SEL Sine Wave Slew Rate (V/µs)

Square Wave

Optimized tPD

≥1500

Preferred

Yes

<1500

Not applicable

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