ADF4378 datasheet(27/84 Pages) AD

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Data Sheet

ADF4378

THEORY OF OPERATION

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Rev. A | 27 of 84

lock detector output on the LKDET pin and the LOCKED bit. The

lock detector output can also be presented on the MUXOUT pin

by programming the MUXOUT bits, Bits[4:0] (see Figure 80). The

MUXOUT, LKDET, SDO, and SDIO output pins is 3.3 V or 1.8 V.

The PFD phase difference must be less than the phase difference

lock window time (tLDWIN) for a set number of PFD cycles before

the lock detector output indicates that the PLL has locked. The

required number of PFD cycles varies if a designer prioritizes lock

detect accuracy or speed. Five loop filter time constants can be

used as an initial estimate of the desired number of PFD cycles, as

shown in Equation 12. The required number of PFD cycles is set

by the LD_COUNT bits, Bits[4:0], as shown in Table 14. For more

information, see Figure 71 and Table 15.

PFD

Cycles= 5×fPFD

2×π×LPBW

(12)

where LPBW = loop filter bandwidth.

Table 14. LD_COUNT Programming

LD_COUNT Bits, Bits[4:0]

PFD Cycles

134

191

270

383

542

767

1085

1535

2171

3071

4343

6143

8687

12287

17376

24575

34754

49151

69510

98303

139021

196607

278044

393215

556090

786431

Table 14. LD_COUNT Programming (Continued)

LD_COUNT Bits, Bits[4:0]

PFD Cycles

1112181

Figure 71. Lock Detector Timing, Bleed Current Disabled

Table 15. Lock Detector Timing, Bleed Current Disabled

Region

Absolute Phase

Difference at PFD

Lock Detector State

> tLDWIN

Low

< tLDWIN

Low, counts PFD cycles

High, ≥ required PFD cycle count

< tLDWIN

High

> tLDWIN

Low (immediately)

When the charge-pump bleed current is enabled, a phase offset is

applied to the PFD inputs. This phase offset (tIDEL) is proportional

to the amount of bleed current programmed in Equation 10 and

Equation 11. Region 3 and Region 4 in Figure 71 and Figure 72

highlight the PFD phase difference that the PLL settles to when the

charge-pump bleed current is disabled or enabled, respectively.

Figure 72. Lock Detector Timing, Bleed Current Enabled

For proper operation of the lock detector, the absolute value of tIDEL

must be less than tLDWIN. The user sets the phase difference lock

window time (tLDWIN) for a valid lock condition with the LDWIN_PW

bit. In most cases, LDWIN_PW must be set to 0. To understand the

relationship between the LDWIN_PW bit and maximum allowable

tIDEL, see Table 16.

Table 16. Maximum tIDEL

LDWIN_PW

tIDEL(MAX)

±150 ps

±250 ps

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